Verification Engineer (UVM/SystemVerilog) 5

Indotronix International Corporation • El Segundo, CA

23h • Onsite

About The Position

Indotronix is seeking an experienced Verification Engineer with expertise in UVM/SystemVerilog. This is an onsite position located in El Segundo, CA, with a first shift from 8:00 AM to 4:30 PM. Possible overtime opportunities may be available. A Bachelor's Degree and an active Secret Clearance are required to start.

Requirements

• Engineering-minded verification engineers, not simply engineers who write test cases.
• 7 or more years of verification experience.
• 2+ years of UVM experience (5+ years acceptable if UVM experience is solid).
• Strong SystemVerilog and UVM experience.
• Self-checking and constrained-random verification; verification planning.
• Debugging; coverage closure.
• Active U.S. security clearance.
• Strong digital hardware fundamentals.
• Sound engineering judgment.
• Ability to work independently with minimal oversight.
• Clear and proactive communication skills.
• Ability to produce high-quality technical documentation.

Responsibilities

• Develop and execute verification plans.
• Implement self-checking and constrained-random verification methodologies.
• Perform debugging and drive coverage closure.
• Produce high-quality technical documentation.
• Take ownership of work and deliver maintainable engineering solutions.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior