TD Memory Quality and Reliability PhD Intern

Intel•Folsom, CA

8d•Hybrid

About The Position

The Technology Development (TD) Quality and Reliability organization supports next-generation semiconductor technologies through silicon-based quality, reliability, and technology-readiness assessments. The Memory Quality and Reliability team collaborates with Design, Device Engineering, Product Development Engineering (PDE), and Yield organizations to develop, characterize, and certify SRAM, Register File (RF), and Fuse technologies for advanced process nodes. Its work supports technology certification and PDK release milestones through memory characterization, silicon data analysis, predictive modeling, and risk assessment. As a TD Memory Quality and Reliability Intern, you will work with experienced engineers to evaluate advanced memory technologies and support technology readiness for future Intel Foundry process nodes. You will contribute to technology certification decisions by analyzing silicon data, developing predictive models, and assessing memory performance across operating conditions. The role provides hands-on experience in memory characterization, silicon data analytics, statistical modeling, and semiconductor technology development. The role is hybrid, allowing employees to split their time between the assigned Intel site and off-site work. The primary location is Folsom, California; additional locations are Santa Clara, California, and Hillsboro, Oregon. The position is a student internship on Shift 1.

Requirements

Currently pursuing a Ph.D. in Electrical Engineering or a related field.
Basic knowledge of semiconductor devices, microelectronics, or integrated circuit design.
Programming or scripting experience using Python or similar languages.
Experience analyzing technical, scientific, or research data through academic projects, research activities, or previous internships.
Cumulative GPA of 3.0 or higher.

Nice To Haves

Coursework, research, or experience in SRAM or memory technologies, semiconductor device physics, VLSI design, statistics, machine learning, data science, or semiconductor process technology.
Experience with Python, Pandas, and NumPy.
Experience with JMP or other statistical analysis tools.
Experience with data visualization and statistical modeling techniques.
Experience with large-scale data analysis and predictive modeling.
Experience in memory architectures, silicon characterization, reliability assessment, or semiconductor test methodologies.

Responsibilities

Analyze silicon characterization data from SRAM, Register File (RF), and Fuse memory test structures to identify performance trends, variability, and potential risks.
Support memory characterization across voltage, temperature, and process conditions.
Perform data analysis, visualization, and reporting using Python, JMP, or similar analytical tools.
Develop and enhance statistical models for Vmin/Vmax prediction and technology-readiness assessments.
Support Silicon-to-Simulation (Sil2Sim) correlation studies and memory characterization methodologies.
Generate technical reports and contribute to technology certification reviews.
Collaborate with Design, Device Engineering, Process Integration, Product Development Engineering, and Yield Engineering teams.
Assist with risk-assessment activities and technology certification milestones.
Present data-driven findings and recommendations to engineering teams and project stakeholders.