Intern - Advanced Packaging TD

Micron Technology • Boise, ID

2d

About The Position

Micron’s Advanced Packaging Technology Development team develops next-generation interconnect technologies designed to improve semiconductor performance, reliability, and advanced packaging capabilities. The Advanced Package TD Process Intern will collaborate with experienced engineers on technologies including hybrid bonding, micro bump technology, Through-Silicon Vias (TSV), and thermal management.

The intern will gain hands-on experience in structured problem-solving, line monitoring, data analysis, experimental design, and project management, contributing to process optimization and yield improvement. The role also involves using AI and Code Assist to develop agent-based solutions that support engineering analysis and process development activities.

Requirements

• Currently enrolled in an accredited university pursuing a Master’s degree or PhD in a semiconductor-related field.
• Expected graduation date no earlier than Fall 2027 and no later than Summer 2028.
• Demonstrated experience with data extraction, statistical analysis, and technical reporting using tools such as JMP or comparable analytics tools.
• Ability to collaborate and communicate technical findings across multifunctional teams.
• Ability to prioritize multiple technical projects, adapt to changing responsibilities, and deliver results within project timelines and resource constraints.
• Experience using AI, Code Assist, or agent-based solutions for technical analysis, engineering workflows, or related applications.

Nice To Haves

• Experience with semiconductor process technologies, including advanced packaging, back-end-of-line (BEOL), advanced interconnect, hybrid bonding, micro bump technology, or TSV.
• Experience with structured problem-solving or decision-making methodologies such as Kepner-Tregoe (KT).
• Academic or research experience related to advanced packaging, interconnect technologies, package thermal performance, or thermal management.
• Experience designing experiments and performing statistical analysis using DoE, JMP, or comparable methods and tools.
• Demonstrated academic, research, or project experience related to advanced semiconductor packaging or interconnect development.

Responsibilities

• Lead structured problem-solving activities using methodologies such as Kepner-Tregoe (KT) to address process and yield challenges.
• Define, complete, and analyze Design of Experiments (DoE) for advanced packaging and interconnect process development.
• Analyze process, line-monitoring, and yield data; develop monitoring methods and critical metrics to support process optimization.
• Present technical findings and collaborate with engineering teams across sites and functional areas.
• Apply AI and Code Assist to develop agent-based solutions that enhance data analysis, engineering workflows, or process monitoring.

Benefits

• Choice of medical, dental, and vision plans.
• Programs to help protect income in case of illness or injury.
• Paid family leave.
• Paid time off.
• Paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Intern