Synthesis Engineer

Qualcomm•Austin, TX

1d•$98,500 - $147,700

About The Position

Qualcomm Technologies, Inc. is seeking a Synthesis Engineer with 0-3 years of experience in Synthesis and LEC. The role involves a strong understanding of Physical Synthesis and Synthesis methodologies using industry-standard tools. Responsibilities include writing timing constraints, Static Timing Analysis (STA), timing closure, and pipelining for performance optimization. Experience with multi-clock domain designs, MCMM synthesis, and low-power design implementation using UPF is required. Proficiency in scripting languages like Perl, Python, and TCL, as well as experience with power optimization techniques such as clock gating, is necessary. The engineer will collaborate with design, DFT, and PD teams for netlist delivery and timing constraint validation, and will handle ECOs and formal verification while maintaining quality metrics.

Requirements

Minimum 0 to 3 years of hands on experience in Synthesis and LEC
Strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
Proficiency in Python/Tcl
Familiar with Synthesis tools (Fusion Compiler/Genus)
Fair knowledge in LEC, LP signoff tools
Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
Bachelor's degree in Science, Engineering, or related field.

Nice To Haves

Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus

Responsibilities

Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
Experience in all aspects of timing closure for multi-clock domain designs.
Familiar with MCMM synthesis and optimization.
Good understanding of low-power design implementation using UPF.
Experience with scripting language such as Perl/ Python, TCL.
Experience with different power optimization flows or technique such as clock gating.
Able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation.
Able to handle ECOs and formal verification and maintain high quality matrix.