Manager, FPGA Synthesis

Altera•Toronto, ON

1d•CA$129,100 - CA$187,000•Hybrid

About The Position

Altera is seeking a Manager, FPGA Synthesis to lead a team responsible for developing and optimizing synthesis technology within the FPGA compiler flow. This role will drive the translation of RTL designs into efficient gate-level implementations, directly impacting performance, power, and area (PPA) across next-generation FPGA platforms. The ideal candidate brings deep expertise in synthesis algorithms and RTL optimization, combined with strong leadership experience and a proven ability to deliver complex EDA solutions at scale.

Requirements

10+ years of experience in FPGA/ASIC design tools, with strong emphasis on synthesis or logic optimization
5+ years of experience managing or leading engineering teams
Deep understanding of logic synthesis, optimization techniques, and mapping algorithms
Strong knowledge of RTL design (Verilog/SystemVerilog/VHDL)
Familiarity with timing-driven synthesis and optimization (timing closure awareness)
Proficiency in C/C++ and software engineering best practices
Experience with Synthesis flows and tools (commercial or in-house)
Experience with FPGA or ASIC design methodologies
Experience with Integration with downstream flows (placement, routing, STA)
Proven ability to lead complex technical initiatives and deliver scalable, high-performance solutions
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Candidates with a PhD are encouraged to apply; in accordance with Canadian hiring practices, relevant experience gained during doctoral studies may be considered toward the required years of experience.

Nice To Haves

Experience with FPGA toolchains (e.g., Quartus, Vivado)
Understanding of FPGA architectures (LUTs, DSPs, BRAM, routing resources)
Experience with advanced optimizations (e.g., retiming, resource sharing, logic restructuring)
Familiarity with scripting (e.g., Python, Tcl) for automation
Background in large-scale, distributed EDA development environments

Responsibilities

Build, manage, and mentor a high-performing synthesis engineering team; drive technical excellence, team growth, and execution.
Lead the development and optimization of synthesis algorithms, including logic optimization, mapping, and netlist generation.
Own and enhance synthesis stages within the FPGA compiler, ensuring seamless integration with placement, routing, and timing (STA) flows.
Drive improvements in performance, power, and area (PPA) through synthesis-driven optimizations and advanced transformations.
Guide efforts in translating high-level RTL (Verilog/SystemVerilog/VHDL) into optimized gate-level representations.
Partner with architecture, placement, routing, and timing teams to align synthesis strategies with FPGA architecture and design goals.
Oversee debugging of synthesis-related issues, including timing bottlenecks, logic inefficiencies, and mapping challenges.
Develop and implement scalable synthesis methodologies, tools, and automation frameworks.