FPGA Development Tools Engineer – Synthesis

Altera•Toronto, ON

1d•CA$129,100 - CA$187,000•Hybrid

About The Position

Altera is seeking a FPGA Development Tools Engineer to join our Synthesis team, focused on advancing the next generation of FPGA compilation technology. In this role, you will develop and enhance synthesis capabilities that transform RTL designs into optimized hardware implementations, directly impacting performance, power, and area (PPA). The ideal candidate brings strong expertise in RTL design and synthesis, combined with a solid software engineering background and a passion for building scalable, high-performance EDA tools.

Requirements

6+ years of experience in FPGA/ASIC design, EDA tools, or related fields
Strong hands-on experience with: Verilog/SystemVerilog or VHDL RTL design and synthesis flows
Proficiency in C/C++ for tool development
Strong understanding of algorithms and data structures
Familiarity with debugging and performance analysis
Understanding of: Logic synthesis and optimization techniques
Understanding of: FPGA or ASIC design flows (synthesis → P&R → STA)
Understanding of: Timing-driven design considerations
Ability to analyze complex systems and develop scalable, high-performance solutions.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Candidates with a PhD are encouraged to apply; in accordance with US hiring practices, relevant experience gained during doctoral studies may be considered toward the required years of experience.

Nice To Haves

Experience with synthesis tools or FPGA toolchains (e.g., Quartus, Vivado)
Knowledge of FPGA architectures (LUTs, DSPs, BRAM, interconnect)
Familiarity with advanced optimizations (e.g., retiming, logic restructuring, resource sharing)
Scripting experience (e.g., Python, Tcl)
Background in compiler development or EDA algorithms
Experience working in large, distributed engineering teams

Responsibilities

Design, implement, and optimize synthesis algorithms to convert RTL (Verilog/SystemVerilog/VHDL) into efficient gate-level representations.
Contribute to the FPGA compiler flow, integrating synthesis with placement, routing, and timing (STA) stages.
Improve quality of results (QoR) by optimizing performance, power, and area through synthesis-driven techniques.
Develop tools and methodologies for analyzing and transforming complex RTL designs.
Work closely with architecture, STA, placement, routing, and validation teams to ensure alignment across the toolchain.
Analyze synthesis results, debug issues (timing, logic structure, mapping), and drive resolution.
Develop internal tools, scripting, and automation to improve synthesis flows and productivity.