About The Position

We are seeking a staff-level Thermal & Thermo-Mechanical Analysis Engineer to lead simulation, modeling, and architectural definition for next-generation AI data center hardware. The role is responsible for the end-to-end thermal integrity of high-power AI systems, including advanced CoWoS silicon-interposer architectures, complex substrate packaging, and high-layer-count data center-class PCBs. The engineer will apply semiconductor thermal-management expertise to develop cooling solutions across the chip, package, PCB, and system stack. Technologies include traditional air cooling, cold plates, direct-to-chip liquid cooling, immersion cooling, microchannel cooling, advanced TIMs, and emerging thermal technologies for future AI compute platforms.

Requirements

  • At least 5 years of industry experience in thermal and structural analysis of semiconductor packages and systems.
  • Proficiency with industry-standard thermal and thermo-mechanical simulation tools, specifically Ansys Icepak and Cadence Celsius.
  • Fluency with Fluent, Star-CCM+, FLOEFD, and RedHawk-SC ET.
  • Proven experience modeling high-density packaging architectures, specifically TSMC CoWoS-L with silicon interposers.
  • Deep understanding of complex package substrates and heavy data center-class PCBs.
  • Hands-on experience analyzing high-power GPU workloads (700 W–1,000 W+) in both steady-state and dynamic transient conditions.
  • Ability to extract, analyze, and present complex simulation metrics, including multi-layer thermal contours and structural warpage profiles.

Nice To Haves

  • Hands-on experience designing physical package layouts and substrate routing using Cadence APD (Allegro Package Designer) or Allegro X.
  • Familiarity with structural analysis tools such as Ansys Mechanical for in-depth finite element analysis (FEA).

Responsibilities

  • Build high-fidelity static and dynamic thermal models for AI workloads spanning silicon, advanced packaging, and system levels.
  • Predict and mitigate structural risks, including warpage, die tilt, thermal stress, and solder-joint reliability (BLR/BGA).
  • Simulate transient thermal behavior under varying data center workloads, calculate time-dependent nodal temperatures, and plot thermal contours.
  • Develop, propose, and implement cooling and mechanical mitigation techniques, such as TIM selection, stiffener rings, and optimized copper balancing.
  • Perform thermal modeling and CFD analysis for die, package, board, and system designs.
  • Develop cooling solutions for high-power AI/HPC devices exceeding 1 kW TDP.
  • Partner with Silicon Architecture, Package Design, and System Hardware teams to co-optimize the thermal-mechanical-electrical envelope.
  • Engage with ODMs and cooling ecosystem partners.
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