Staff/Sr. Staff RTL Design Engineer - QGOV
About The Position
As a Design Engineer, you’ll play a critical role in shaping cutting-edge digital designs. Your responsibilities will include: Micro-Architecture: Designing micro-architecture for both simple and complex digital, interface blocks. RTL Development: Developing RTL (Register Transfer Level) code using industry best practices. This includes handling multi-clock designs, high-frequency requirements, low power, and low latency considerations while ensuring high performance. Debugging and Post-Silicon Bring-Up: Troubleshooting and debugging issues during the development process and supporting post-silicon bring-up activities. Documentation: Creating comprehensive design documentation to ensure clarity and maintainability. Design Optimization: Optimizing designs for key metrics such as area, power, and performance. Cross-Functional Collaboration: Collaborating with cross-functional teams, including DFT (Design for Testability), Implementation, Verification, Emulation, and Firmware teams. Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Requirements
- 6-10+ years of work experience with RTL/FPGA design (Verilog, System verilog), embedded system architecture and Verification
- Bachelor's degree in computer science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
- OR Master's degree in computer science, Electrical/Electronics Engineering, Engineering, or related field and 5+ year of Hardware Engineering or related work experience.
- OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
- Must be in San Diego full time, 5 days a week
- Must be a U.S. citizen and eligible to receive a U.S. Government security clearance
Nice To Haves
- Positive Attitude: Bring a fun-loving attitude and a passion for inclusively solving problems.
- 5+ years of ASIC design experience
- System Verilog Design, Linting, CDC, Synthesis (FPGA and ASIC)
- Building the test suites for design validation
- Understanding of Emulation and prototyping flows for the design and validation in Lab is a big Plus.
- Experience with designing complex digital logic blocks and sub systems (CPU, GPU, DSP, Always on Systems, Digital interfaces (PCIe, UART, I2c, DDRx, SPI, USB).
- Knowledge of ISAs (Instruction Set Architectures) such as ARM THUMB or RISC-V.
- Understanding of processor or microcontroller system design.
- Experience with designs spanning multiple power domains and clock domains.
- Proficiency in scripting or automation languages like Python or Perl.
- Familiarity with state-of-the-art industry-standard digital design tools.
- Awareness of challenges faced when working with lower node technologies.
Responsibilities
- Designing micro-architecture for both simple and complex digital, interface blocks.
- Developing RTL (Register Transfer Level) code using industry best practices, handling multi-clock designs, high-frequency requirements, low power, and low latency considerations while ensuring high performance.
- Troubleshooting and debugging issues during the development process and supporting post-silicon bring-up activities.
- Creating comprehensive design documentation to ensure clarity and maintainability.
- Optimizing designs for key metrics such as area, power, and performance.
- Collaborating with cross-functional teams, including DFT (Design for Testability), Implementation, Verification, Emulation, and Firmware teams.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package is designed to support your success at work, at home, and at play.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
