Staff Silicon Photonics Design Engineer

Neurophos • San Mateo, CA

1d • Onsite

About The Position

The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of computing!
We are seeking an experienced Silicon Photonics Designer to join our SiPh team. In this role, you will own the end-to-end design, simulation, layout, and characterization of passive silicon photonic components—including edge couplers, grating couplers, and hybrid/directional couplers—targeting a high-performance co-packaged optics system for artificial intelligence Inference applications. You will work directly with renowned foundry partners and cross-functional teams in VLSI, packaging, systems, and testing to bring photonic designs from concept to production-ready silicon.

Requirements

• M.S. or Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline
• 3+ years of hands-on silicon photonics design experience in an industry setting (or equivalent depth of graduate research with demonstrated tapeout and measurement record).
• Proven expertise in designing passive silicon photonic components: edge couplers, grating couplers, directional/hybrid couplers, waveguides, and splitters on SOI platforms.
• Proficiency with photonic simulation tools: FDTD, BPM, FDE, CMT, and EME solvers (Ansys Lumerical Suite, Synopsys Rsoft, Photon Design, or equivalent) and circuit-level simulation.
• Demonstrated PIC layout experience using Cadence Virtuoso, KLayout, and/or Python-based parametric layout frameworks (GDSFactory, IPKISS, or similar) for GDS generation.
• Familiarity with electro-optic device design (Lasers, MZM, ring modulator, Ge photodetector) to enable holistic PIC integration.
• Experience with at least one commercial silicon photonics foundry PDK and tapeout flow (TSMC, GlobalFoundries – GF Fotonix /AMF, Tower, AIM Photonics, or equivalent).
• Programming proficiency in Python and/or MATLAB for simulation automation, data analysis, and statistical evaluation of device performance.
• Working knowledge of datacom or coherent transceiver link architectures and system-level optical specifications.
• Experience with coherent PIC design elements: IQ modulators, optical hybrids (90° hybrid), polarization splitters/rotators, and balanced detector integration.

Nice To Haves

• Direct foundry interface experience with silicon photonics platforms—including DRC/LVS sign-off, OPC coordination, and MPW/dedicated wafer shuttle management.
• Full tape-out ownership: concept → simulation → layout → DRC clean → tapeout → wafer receipt → measurement → design iteration.
• Strong knowledge on high-speed optoelectronics device design and measurement
• Hands-on optical measurement skills: coupling loss/insertion loss characterization, swept-wavelength spectral measurements, polarization-dependent loss (PDL) measurements.
• Familiarity with SiN photonics platforms (low-loss, broadband) for edge coupler or wavelength-routing applications.
• Good knowledge on wafer backend process and optical packaging: lensed-fiber or FAU edge-coupling assembly, active alignment, and fiber attachment processes for photonic modules.
• Exposure to co-packaged optics (CPO) architectures, flip-chip or die bonding of III–V laser sources, or heterogeneous photonic integration.
• Experience with automated measurement scripting (Python GPIB/VISA frameworks, automated wafer-level or die-level test stations).
• Publications, patents, or conference presentations (OFC, ECOC, SPIE Photonics West) demonstrating silicon photonics design contributions.

Responsibilities

• Design, simulate, and optimize passive silicon photonic building blocks: edge couplers (inverse tapers, spot-size converters), grating couplers (1D/2D, chirped/apodized, dual-polarization), and hybrid/directional/multimode-interference (MMI) couplers for compact PIC designs.
• Develop waveguide routing, splitters, polarization splitters/rotators (PSR), crossings, and other PIC sub-elements with explicit attention to insertion loss, return loss, bandwidth, polarization dependence, and process variation tolerance.
• Conduct FDTD, eigenmode expansion (EME), and circuit-level simulations using Ansys Lumerical, Synopsys Optsim, or equivalent tools; perform tolerance and process-corner analysis to ensure robust yield across foundry runs.
• Implement PIC layouts using Cadence Virtuoso, KLayout, or script-based parametric design flow, generate DRC-clean GDS for submission to foundry, including DRC/LVS sign-off, design review, and mask data preparation.
• Manage and drive tapeout processes with mainstream SiPh foundries, or equivalent silicon photonics PDKs
• Interface directly with foundry process engineers to negotiate design rule waivers, understand process corners, and resolve integration challenges throughout the design cycle.
• Define and execute design-of-experiments (DOE) test chip strategies to characterize process sensitivities and close the loop between simulation and measurement results.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO. No rigid vacation banks, just a focus on delivery.
• 401(k) matching and stock option opportunities to ensure our success is your success.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior