Staff Layout Design Engineer

Qorvo • Tallahassee, FL

3d • $144,300 - $187,600

About The Position

In this position, you will work closely with design engineering groups to complete the layout and verification of high-performance Switches, Power Management Devices, and Integrated Products using Cadence Virtuoso XL and Mentor’s Calibre tools.

Requirements

• Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience
• Ability to layout analog circuitry in a size/time constrained environment
• Understand layout techniques such as common centroid, matching, isolation, and the use of dummy devices
• Ability to solve design problems using technical skills, intuition, and creativity
• Proficiency in floorplanning and assembly from block to full chip level
• Working knowledge of Cadence and Mentor Verification tools
• Strong LVS troubleshooting and debug skills
• Demonstrated ability to work individually and in a team-orientated environment

Nice To Haves

• BSEE/BS Engineering Technology or related program
• Comfortable with CMOS and SOI technologies across multiple foundry PDKs
• Demonstrated ability to contribute ideas for improved schematic and layout interaction
• Schematic entry for dummy devices, resizing devices, and debugging LVS issues.

Responsibilities

• Work closely with design engineers to ensure proper circuit performance
• Design analog and RF layout
• Understand device matching techniques
• Excellent teamwork skills, including written and verbal communications, with both local and remote design teams
• Exceptional layout planning and integration skills from small block to full chip

Benefits

• Competitive base salary commensurate with experience: $144,300 - $187,600, relevant for the California Bay Area (subject to change dependent on physical location)
• Total Rewards package

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree