Staff IC Packaging Engineer - Mechanical Simulation

Qualcomm • San Diego, CA

19d • $160,200 - $240,200

About The Position

This position is part of Qualcomm’s Integrated Circuits (IC) package engineering process team. The engineer will use finite element analysis (FEA) expertise to support current and future chipsets, working closely with design, new product introduction (NPI), and Chip-Package Interaction (CPI) teams. The role provides mechanical simulation support for high-volume manufacturing (HVM) and advanced packaging technologies.

The engineer develops mechanical FEA models, preferably using ANSYS APDL and Workbench, maintains APDL macros and workflows, establishes FEA methodologies and best-known methods (BKMs) for test correlation and material characterization, and performs stress and mechanical analyses for IC package designs and failure prediction. The work includes warpage and stress analysis, solder joint reliability (SJR) prediction, package assembly process simulation, and CPI analysis. The role uses advanced FEA techniques, including sub-modeling, contact analysis, and nonlinear analysis, as well as material characterization and testing procedures. A foundation in silicon, package, and board-level interconnect technologies is needed. Strong communication, project focus, and execution skills are expected.

The position may require flexible hours to collaborate across APAC and the U.S., as well as occasional domestic and international travel. Qualcomm offers a pay range of $160,200 to $240,200, a competitive annual discretionary bonus program, potential annual RSU grants subject to eligibility, and a competitive benefits package.

Requirements

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field and 4+ years of System/Package Design/Technology Engineering or related work experience; or a master's degree in one of these fields and 3+ years of related experience; or a Ph.D. in one of these fields and 2+ years of related experience.
• Strong communication, project focus, and execution skills.
• Ability to work flexible hours to support collaboration across APAC and the U.S.
• Understanding of the fundamentals of silicon, package, and board-level interconnect technologies.

Nice To Haves

• Ph.D. in Mechanical Engineering, Material Science, Electrical/Microelectronics, or a related engineering field.
• 6+ years of combined experience in finite element modeling and analysis for IC electronic packages and interconnects.
• 3+ years of experience with ANSYS APDL and/or Workbench.
• 4+ years of direct work experience in the semiconductor and IC microelectronic packaging industry.
• Experience with IC electronic packaging structures, assembly processes, reliability testing and analysis, CPI, package-board interaction, and design of experiments.
• Solid understanding of IC packaging materials and their thermo-mechanical behaviors.
• Hands-on FEA experience developing and improving BKMs for predictive modeling to guide package mechanical design and support manufacturing and reliability needs.
• Experience with material characterization and testing, including developing test methods to improve package FEA model accuracy and prediction correlation.
• Research and publications in FEA predictive modeling, warpage, CPI, and solder lifetime prediction.
• Experience using internal AI tools to accelerate APDL coding and improve simulation workflows.
• Strong analytical skills and a proven track record of project execution; excellent communication and presentation skills.
• Self-starter with high motivation and a strong commitment to product success.
• Willingness to travel domestically and internationally occasionally.

Responsibilities

• Provide mechanical simulation support for current high-volume manufacturing and advanced packaging technologies.
• Develop mechanical FEA models, preferably using ANSYS APDL and Workbench.
• Maintain APDL macros and simulation workflows.
• Establish FEA methodologies and best-known methods for test correlation and material characterization.
• Perform stress and mechanical analyses for IC package designs and failure prediction.
• Conduct warpage and stress analysis, solder joint reliability prediction, package assembly process simulation, and chip-package interaction analysis.
• Use advanced FEA techniques, including sub-modeling, contact analysis, and nonlinear analysis.
• Perform or support material characterization and testing procedures.
• Collaborate with design, NPI, and CPI teams.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants; employees on sales-incentive plans are not eligible for the annual bonus.
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior