Staff Engineer, RTL

Samsung Semiconductor•San Jose, CA

6d•$163,000 - $253,000•Onsite

About The Position

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy.

Requirements

Bachelors degree 10+ years of experience or Masters degree 8+ years, PhD with 5+ years of experience.
Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
Familiarity with SystemC or transaction-level modeling.
Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Nice To Haves

Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
Exposure to low-power design and thermal management.
Exposure to power macromodeling, power estimation flows, or architectural power analysis.

Responsibilities

Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
Define power-relevant functional states (transaction/state-based abstraction).
Support trace-driven power modeling, aligned with C/SystemC workload traces.
Perform synthesis-assisted calibration using average and worst-case power anchors when available.
Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
Contribute to scalable IP-wise composition for full-system power simulation.