Staff Engineer, Digital Design Engineering

Analog Devices•Beaverton, OR

About The Position

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $24 billion in FY25 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). Join our Automotive OpenGMSL Team as a Staff Digital Design Engineer! We are seeking an experienced, self-motivated, and passionate engineer to lead, architect, and design cutting-edge products for Automotive SerDes applications. OpenGMSL (Gigabit Multimedia Serial Link) is the leading high‑speed in‑vehicle serial link technology in the automotive industry. It enables safe and secure transport of video and data while significantly reducing the cost, weight, and complexity of vehicle cable harnesses. Our extensive portfolio of products is in full production, with millions of vehicles worldwide relying on it daily. OpenGMSL offers cost-effective video and data transport and bridging for various applications, including basic information displays and rearview cameras in mass-market vehicles, safety-critical cameras in autonomous vehicles, and high-resolution touch screens in high-end vehicles. Beyond automotive, OpenGMSL solutions are widely used in industrial and medical systems as well as in growing robotics applications. The position is based in Beaverton, Oregon, or Colorado Springs, Colorado.

Requirements

MSEE or Equivalent: Master's degree in Electrical Engineering or equivalent with 5+ years of relevant experience or PhD with 3+ years of relevant experience.
Digital Design: Experience designing and verifying complex digital systems using Verilog/SystemVerilog.
System Architecture & Implementation: Demonstrated ability to architect and plan designs at the system level, translating high-level product concepts into robust design implementations.
Communication Skills: Clear and concise written and verbal communication skills, with team working experience and a proactive approach to problem-solving.
SerDes & Communications Expertise: Understanding of communication theory, high-speed SerDes transceiver architectures, and video/data transport.
Design Trade-Offs & Physical Implementation: Solid understanding of digital and analog design trade-offs, with experience in timing analysis, power estimation, physical design, and DFT concepts.
Lab & Silicon Debug Experience: Hands-on experience with silicon bring-up and debug

Nice To Haves

SerDes Standards and Protocols: Expertise in high-speed SerDes standards and protocols, including Ethernet, USB, PCIe, and/or video (DisplayPort, CSI/DSI, HDMI)
Technical Standards Experience: Experience authoring SerDes technical standards and/or participating in industry standards committees.
Behavioral Modeling: Experience with behavioral modeling, including verification of mixed-signal systems with behavioral modeling.
Team Leadership: Experience leading teams and/or projects.

Responsibilities

Digital Architecture and Design: Architect and design digital blocks and subsystems of complex high-speed SerDes ICs, including Gigabit‑speed serial interfaces and video and data routing solutions.
Develop Next‑Generation Technologies: Architect, develop, and actively contribute to next-generation OpenGMSL technologies, including the definition of new architectures and participation in the development of OpenGMSL technical standards for future product generations.
Specification Ownership: Write detailed block and subsystem-level specifications for design and implementation.
RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems, and top‑level designs.
Verification and Coverage Closure: Develop block‑level testbenches, verify block functionality, and collaborate with verification teams to achieve full‑chip verification and coverage closure.
Digital Backend: Perform block‑ and top‑level linting, CDC analysis, and power analysis. Assist with synthesis constraints and timing closure.
Mixed‑Signal Integration: Communicate closely with mixed-signal designers and verification engineers to support mixed‑signal simulations and real‑number modeling across the analog/digital boundary.
Documentation and Design Reviews: Prepare technical documentation and lead architecture, design, and peer reviews.
Lab Evaluation and Debug: Support silicon bring‑up, characterization, and debug activities.
Cross‑Functional Collaboration: Collaborate across analog, digital, verification, test, and product definition teams to define requirements, support production test development, and ensure successful product execution.
Technical Leadership: Provide technical leadership for complex SerDes subsystems and products.