Staff Chip Security Architect, AI Accelerators

Qualcomm•San Diego, CA

3d•$134,800 - $202,200

About The Position

Qualcomm Technology Inc.’s Dragonfly AI accelerator cards provide the backbone of an enhanced AI experience by shifting the AI workloads away from generic processors and onto specialized NPU cores that provide faster execution times, shorter latencies, and lower power consumption. These accelerators bear the responsibility of processing valuable user and model data – meaning that security is a critical product requirement that must be achieved to guarantee the products’ success in the market. We are seeking a talented security architect to join the Dragonfly security team to design and implement the security architecture for the next generation of AI accelerator chips design for use in datacenter settings. You will determine the security requirements for an AI accelerator chip, work with other architects to develop and document an architecture to meet those requirements, and work with other developers to prototype / implement major components of that architecture.

Requirements

Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience.
Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience.
PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience.
2+ years of work experience with Programming Language such as C, C++, Java, Python, etc.
A Bachelor's degree in Engineering, Information Systems, Computer Science, or related field, and 7+ years of experience in product security or a related field. Work experience gained by successfully completing a Master’s or Doctoral degree will be taken into consideration.
Experience in the design and implementation of access control and isolation systems in complex embedded systems involving multiple tenants / security domains.
Proficiency in the C programming languages with experience in developing embedded security systems.
An understanding of the principles and common implementations of device attestation systems.
An understanding of practical cryptography as it applies to the development of mutually trusted components that must communicate at high-speeds over untrusted networks.
Excellent written and verbal communication skills.

Nice To Haves

A Master’s degree with a security specialization in Engineering, Information Systems, Computer Science, or related field.
Experience in the architecture and design of AI accelerator systems, including the use of optimized NPU architectures and high-bandwidth data paths over untrusted networks.
Experience in developing security solutions for PCIe devices, including the trusted device assignment, TDISP, IDE, PF / VF isolation, and DMA isolation.
Experience in developing confidential compute solutions for datacenter products as defined by the Open Compute Project (OCP), the Confidential Computing Consortium (CCC), and the Arm CCA Security Model.
Experience in developing secure out-of-band management systems for devices deployed in datacenters, including an understanding of the Caliptra attestation hardware block.
Experience in the development of AI accelerator systems and an understanding of the processes in an AI model computation.

Responsibilities

Define and document the baseline security requirements for an AI accelerator chip.
Define and document the security requirements for an AI accelerator chip that meets confidential compute requirements including attestation and workload isolation.
Define and document the security requirements for an AI accelerator chip that uses scale-up and scale-out networks for accelerated communication between processors.
Define and document the security requirements for an AI accelerator chip which is under the control of an out-of-band management server through a Board Management Controller (BMC).
Define and document an architecture that meets the security requirements for the product.
Work with developer teams to prototype, implement, and test security critical parts of the chip architecture.
The role combines security architecture work with hands-on prototyping and implementation.