PCB Design Engineer, Sr Staff

d-Matrix • Santa Clara, CA

1d • Hybrid

About The Position

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. As a Sr. Staff PCB Layout Design Engineer, you will be the lead architect of the physical medium that connects our breakthrough AI silicon to the world. At d-Matrix, our "Corsair" platforms push the boundaries of signal density and power delivery. You will own the layout of high-complexity, high-layer-count PCBAs (20+ layers), ensuring that 112G/224G SerDes signals remain pristine and that thousands of Amps are delivered across the board with minimal loss. In this senior leadership role, you will also serve as the custodian of our Design Methodology, driving the automation, tooling, and rigorous constraint management processes that allow us to scale our hardware development with high precision and speed.

Requirements

• Education: BS in Electrical/Electronic Engineering or equivalent practical experience.
• Experience: 12+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators.
• Mastery of Constraints: Expert-level proficiency in Cadence Allegro Constraint Manager, including the setup of complex T-junctions, differential pair phase-tuning, and Z-axis delay matching.
• Automation Skills: Proven ability to write and deploy SKILL scripts or utilize Allegro’s API to automate design audits and layout routines.
• Technical Depth: Deep understanding of high-speed routing (back-drilling, via-in-pad, and skip-vias).
• Experience with HDI (High-Density Interconnect) and ELIC (Every Layer Interconnect).
• Proven track record of successfully routing 112G SerDes and complex DDR5/HBM interfaces.

Nice To Haves

• Experience establishing a Library Management System and standardized footprint/padstack creation processes.
• Familiarity with PLM/PDM integration for managing layout releases and ECO (Engineering Change Order) workflows.
• Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs.

Responsibilities

• Full-Cycle System Layout: Lead the layout for high-complexity AI accelerator cards (PCIe form factors) and massive system baseboards.
• Constraint Management & Process: Architect and manage the Constraint Manager (CM) hierarchy within Cadence Allegro. You will define the "Source of Truth" for high-speed routing rules, physical spacings, and electrical constraints, ensuring they are consistently applied across all project phases.
• Tooling & Automation: Drive productivity by developing or implementing automation scripts (SKILL, Python, or TCL) to streamline repetitive layout tasks, DRC checks, and report generation.
• High-Speed Mastery: Execute layout for ultra-high-speed interfaces, including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects.
• Power Delivery Optimization: Work with Power Engineers to implement complex PDN strategies, including multi-phase VRM layouts and optimized decoupling capacitor placement for high-TDP ASICs.
• Stack-up & Material Science: Drive the definition of PCB stack-ups, selecting advanced low-loss materials (e.g., Megtron 7/8) and managing hybrid build-ups.
• DFx & Manufacturing: Act as the primary interface with PCB fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 101-250 employees