Sr. Staff Firmware Engineer (Secure Boot & Real Time Platform)
About The Position
As a Sr. Staff Firmware Engineer, you will design and implement the mission-critical secure boot-chain, flash partition architecture, and hardware-enforced isolation layers for our next-generation Software-Defined Vehicle (SDV) platform. This is a pure embedded C engineering role focused on high availability, extreme durability, and fail-safe robustness. You will architect the boundaries where bare silicon meets low-level execution environments, developing a zero-downtime system that handles concurrent inter-core communication and guarantees autonomous systems never experience a field failure.
Requirements
- Hardware Root of Trust & Security: Configure hardware-based cryptographic enclaves (HSMs, TPMs, or ARM TrustZone).
- Develop firmware controls for secure key storage, device attestation, and anti-rollback protection via eFuses or secure flash memory.
- High-Performance Inter-Core Communication: Design, implement, and optimize low-latency Inter-Process Communication (IPC) and Inter-Core Communication (ICC) mechanisms utilizing shared memory architectures, hardware semaphores, and zero-copy data paths.
- High-Durability Storage Systems: Package and deploy low-level block drivers and fault-tolerant flash file systems (e.g., eMMC, UFS, QSPI).
- Implement advanced wear-leveling and delta compression techniques to maximize flash lifespan and minimize bus bandwidth.
Nice To Haves
- Pure Firmware Development: Write high-performance, deterministic embedded C tailored for resource-constrained environments, ensuring freedom from interference (FFI) and tight control over task scheduling.
- Defensive Engineering: Protect low-level execution paths against physical and electrical attack vectors, including voltage manipulation, clock glitching, and unauthorized side-channel access.
- Low-Level Hardware Integration: Lead physical hardware bring-up and verification in the lab using JTAG/SWD debuggers, logic analyzers, and oscilloscopes.
- Validate low-level memory protections, security states, and low-to-high speed peripheral/bus interference
Responsibilities
- Architect the Secure Boot-Chain: Design and optimize the multi-stage secure boot sequence—from immutable mask ROM and Primary Bootloaders (PBL) to Secondary Bootloaders (SBL/U-Boot)—ensuring execution integrity.
- Hardware-Enforced Isolation: Implement and configure advanced hardware firewall technologies (such as NXP xRDC / XRDC4) and core-level Memory Protection Units (MPUs).
- Manage Cohort/Domain IDs, Master Domain Assignment Controllers (MDAC), and Peripheral Access Controllers (PAC) to achieve strict resource isolation, peripheral partitioning, and fault domain segregation.
- Fail-Safe A/B Update Layouts: Implement atomic A/B firmware slot update schemes and dual-bank partition architectures.
- Design the low-level state machines for partition switching, background flashing, and automatic runtime fallback loops.
Benefits
- health_insurance
- dental_insurance
- vision_insurance
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
