Sr. Staff ASIC Design Engineer

Tensordyne•Sunnyvale, CA

5d•Hybrid

About The Position

As a Sr. member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of high-performance AI ASICs. These ASICs closely couple novel computational accelerator units, compute, interconnects, networking and 3rd-party IP blocks as needed to redefine the next generation of tokenomics for inference.

Requirements

10+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.
Experience in IP integration, specifically CPU IP into SoC.
Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
Familiarity with AMBA/APB/AXI Protocol
Familiarity with processor peripheral interfaces like SPI, eMMC, MII, GPIO, I2C ....
Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.
Familiarity with low power design.
UPF flow for defining power intent of chips with multiple power domains
Self-starter and highly-motivated to work in a dynamic start-up environment.
B.S. (M.S. preferred) degree in Electrical or Computer engineering.

Nice To Haves

Previous experience with timing closure at high frequencies is a plus.
Interest to explore AI architectures for convolution, transformer and other kinds of workloads

Responsibilities

Author micro-architecture specifications and participate in specification and test plan reviews.
Architect and implement complex RTL designs.
Scope third party IP requirements and solicit vendors.
Integrate CPU and other relevant IPs into the CPU sub-system.
Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.
Analyze code coverage and provide feedback to the verification team to achieve coverage closure.
Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab.