Sr. Semiconductor Test Engineer

Mythic • Austin, TX

9d • $140,000 - $270,000

About The Position

Mythic is seeking a hands-on semiconductor test engineer to own production testing across the full silicon lifecycle, from bring-up and characterization through Wafer Sort, Final Package Test, and high-volume manufacturing. The role is a build role focused on defining how Mythic tests and ships silicon, including test methodology, coverage strategy, screening philosophy, release criteria, test programs, and supporting infrastructure. The engineer will set strategy while also writing code, debugging hardware, and analyzing manufacturing data, in collaboration with design, DFT, product engineering, reliability, and manufacturing teams.

The position owns Mythic’s end-to-end production test strategy and programs for new silicon products, including development, debug, production release, and optimization. It also encompasses silicon bring-up and characterization, correlation, guardbanding, test transfer into manufacturing, yield and quality analysis, and technical coordination with OSATs, foundries, and ATE vendors. The role requires balancing test coverage, cost, test time, quality, and ramp schedules, while building infrastructure, automation, and analytics for production test and yield learning.

Requirements

• At least 5 years of experience in semiconductor test engineering, product engineering, or production test development.
• Hands-on ownership of Wafer Sort and Final Package Test.
• Experience developing, debugging, and releasing test programs on ATE platforms in production.
• Ability to convert and translate test patterns from STIL, WGL, and VCD into ATE-specific pattern formats.
• Solid grounding in manufacturing test flows, device screening, test coverage, guardbanding, and outgoing quality.
• Experience taking silicon through bring-up, characterization, yield ramp, and production release.
• Strong debugging skills and fluency with manufacturing test data.
• Experience working with design, DFT, product, reliability, and operations teams.

Nice To Haves

• Experience testing mixed-signal or analog silicon, including trim and calibration.
• Experience with AI, accelerator, or high-performance compute silicon.
• Experience with Advantest, Teradyne, or similar ATE platforms.
• Experience with probe cards, load boards, hardware interfaces, and test hardware debugging.
• Experience with DFT structures such as scan, MBIST, and boundary scan.
• Experience managing OSATs and other external manufacturing partners.
• Experience with scripting, automation, and test-data analysis, such as Python, JMP, or yield-analysis tools.
• A track record of reducing test time and improving yield and correlation during ramp.

Responsibilities

• Own end-to-end production test strategy across Wafer Sort, Final Package Test, characterization, screening, and volume ramp.
• Develop, debug, release, and optimize test programs for new silicon products.
• Define test methodology, coverage strategy, screening philosophy, and release criteria.
• Perform silicon bring-up and characterization, correlation, guardbanding, and test transfer into manufacturing.
• Analyze yield and quality to identify systematic failures and escapes and drive them to root cause.
• Work day to day with OSATs, foundries, and ATE vendors to deploy and sustain test flows.
• Manage tradeoffs among test coverage, cost, test time, quality, and ramp schedule.
• Build infrastructure, automation, and analytics for production test and yield learning.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed