Sr. Principal VLSI/ ASIC Design Engineer

Hewlett Packard Enterprise•Sunnyvale, CA

3d•$181,000 - $367,000•Hybrid

About The Position

The Sr. Principal VLSI/ASIC Design Engineer is responsible for the architecture, RTL design, implementation, and analysis of complex VLSI components and system-on-chip (SoC) solutions. The role contributes to early-stage architecture and design exploration and carries concepts through detailed design implementation for networking, compute, and other complex SoC applications. The engineer serves as a recognized technical authority in ASIC and VLSI design, influencing product strategy, technology roadmaps, architectural direction, and implementation methodologies across organizations and business units. The position calls for technical leadership, innovation, cross-functional collaboration, and mentoring while delivering high-quality, scalable, production-ready designs. This role is designed as hybrid, with an expectation to work an average of two days per week from an HPE office. The position is in Engineering, at job level TCP_06. The stated California base salary range is USD 181,000–367,000 annually; variable incentives may also be offered. Actual offers may vary based on location, experience, education, training, and skill level.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered.
Typically 11 or more years of experience in ASIC, VLSI, SoC, or related hardware design.
Demonstrated experience designing complex RTL blocks for networking, compute, communications, storage, or other advanced SoC applications.
Experience leading architecture and design exploration through RTL implementation and product integration.
Advanced knowledge of ASIC and VLSI design principles, digital logic, RTL design, and SoC development.
Proven experience developing complex RTL using Verilog, SystemVerilog, or comparable hardware description languages.
Understanding of ASIC development flows, including architecture, microarchitecture, RTL coding, synthesis, timing analysis, physical design interaction, and design signoff.
Experience with design modeling, simulation, performance analysis, and empirical evaluation methodologies.
Strong analytical, problem-solving, and technical decision-making skills.
Ability to evaluate design alternatives and make recommendations based on performance, power, area, cost, risk, and schedule.
Experience defining and improving design methodologies, tools, automation, and engineering practices.
Demonstrated innovation, including developing or adopting new technologies, methodologies, or design practices.
Strong written and verbal communication skills, including the ability to explain complex technical concepts to technical and executive audiences.
Ability to communicate architectural proposals, design plans, tradeoffs, risks, and results effectively.
Proven ability to influence decisions across business units, functions, senior leadership, external partners, and industry organizations.
Strong collaboration skills and experience working effectively across geographically distributed, cross-functional teams.
Ability to mentor engineers and provide technical direction without direct management responsibility.

Nice To Haves

Design verification experience is highly desirable but not required.
Experience with networking ASICs, data-processing units, switching, routing, acceleration, storage, or high-performance computing architectures.
Experience with high-speed interfaces, packet-processing pipelines, memory subsystems, interconnects, or performance-critical datapaths.
Familiarity with formal verification, constrained-random verification, coverage methodologies, or verification planning.
Experience with low-power design, clock-domain crossing, reset-domain crossing, DFT, and design-for-reuse methodologies.
Knowledge of industry standards and leading-edge ASIC implementation technologies.
Experience working with outsourced development partners, IP vendors, foundries, or semiconductor suppliers.

Responsibilities

Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
Define architectural approaches, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps.
Design, develop, and modify complex RTL blocks using industry-standard hardware description languages and design practices.
Drive RTL implementation from architectural definition through synthesis, physical implementation support, timing closure, and production readiness.
Analyze design tradeoffs involving performance, power, area, scalability, reliability, and time to market.
Develop and evaluate VLSI components and hardware systems across multiple platforms and product organizations.
Conduct design reviews and evaluate product designs for compliance with architecture, implementation guidelines, quality standards, and industry best practices.
Establish operating data and performance expectations through analytical modeling, simulation, prototyping, and experimental evaluation.
Provide data-driven feedback to improve product quality, reduce design risk, and mitigate potential product failures.
Contribute to organization-wide ASIC design architectures, methodologies, and standards.
Create integration plans for incorporating new technologies, IP, design practices, and implementation improvements into existing architectures.
Identify emerging technologies, innovations, tools, and external partnerships that support business objectives and technology roadmaps.
Review material specifications, hardware designs, electrical component requirements, and related technical documentation.
Collaborate with architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, and external development teams.
Influence technical decisions made by business leadership, development partners, suppliers, and industry standards organizations.
Provide technical leadership for significant projects and programs, connecting teams across functions around common objectives.
Mentor less-experienced engineers and promote design innovation, engineering excellence, and knowledge sharing.
Serve as an internal authority on ASIC and VLSI engineering, providing consultation across organizations and business units.
Make substantial technical contributions to significant HPE products, programs, or strategic architectural initiatives.
Deliver lasting improvements in time to market, product quality, cost reduction, scalability, and customer value.
Contribute to the broader technical community.