Sr Principal Design Engineer

Cadence Systems•San Jose, CA

1d•Onsite

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links. The successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure.

Requirements

Mixed-signal circuit design fundamentals
Mixed-signal circuit design and verification flows
Cadence analog design environment
Basic signal processing concepts
Excellent verbal and written communication skills
Ph.D. EE degree with 5+ years or MS EE. degree with 7+ years of mixed signal design industry experience in advanced process technologies

Nice To Haves

Serial link design techniques
Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
MATLAB or C to facilitate architecture development
Hardware description languages such as SystemVerilog or VerilogA for functional model development
Scripting languages such as Perl or Python for automation
Silicon validation testing knowledge and experience

Responsibilities

Contribute to all mixed-signal design, verification, and testing aspects.
Circuit design and development from a high-level architectural specification.
Post-silicon test plan development and execution.
Collaboration with the digital team to achieve functional and performance closure.