Principal Engineer -Design
About The Position
Microchip’s Communications Business Unit (CBU) is a premier supplier of 100Gbps+ Optical Networking and Connectivity Solutions for Telecom and Hyperscale Data Center Networks. Our state-of-the-art devices power high-bandwidth, cloud-based applications including streaming services, social media platforms, and video conferencing worldwide. The CBU Product Development team drives the full semiconductor R&D lifecycle—from initial concept, design, and implementation to embedded software integration, system validation lab testing, and mass-market production release. Working with the latest tools and methodologies in advanced process nodes, our experienced team delivers industry-leading network devices. We are seeking a Principal Engineer to join the CBU Product Development team. In this role, you will lead the digital design, DFT, physical implementation, and static timing analysis (STA) of integrated circuits at both the block and top chip levels. Working alongside our implementation team on advanced technology nodes, you will drive RTL-to-pre-layout netlist generation and own STA signoff across multiple macros, subsystems, and full-chip designs using industry-standard Cadence and Synopsys synthesis suites.
Requirements
- Bachelor’s or Graduate Degree in: Computer Sciences, Electrical/Electronics/VLSI Engineering
- 10 years of experience in synthesis, STA and Formal Verification with mainstream tools.
- Excellent analytical and debugging skills and the ability to proactively solve issues
- Strong coding skills and scripting skills (TCL, Perl or Python).
- Proven ability to thrive on, learn and adapt to new methodologies and technologies
- Hands on experience in RTL Design, synthesis, low-power logic insertion using UPF/CPF and STA signoff of Macro’s and SoC Level.
- Good understanding of timing models, DFT, libs, hierarchical budgeting flows.
- Hands-on to deliver solutions to critical design and execution issues related to synthesis.
- Tapeout experience of 1 or more projects with 16nm or smaller silicon process technologies
- Hands-on experience with synthesis tools like Cadence Genus OR Synopsys-DC/FC.
- Good verbal and written communication skills in English, strong interpersonal skills
Responsibilities
- Responsible to develop macro constraints (Synthesis, STA & Layout), ram generations, flow configuration for High-speed complex macros and Subsystems.
- Responsible for STA sign off for all levels of design hierarchy for multiple modes and multiple corners (MMMC).
- Responsible to develop/understand flow and methodology for doing RTL Synthesis.
- Ability to pick up new flows, learn on the job and influence QOR is a must.
- Co-work with RTL and DFT engineers and interact with project teams to ensure the right constraints/deliverables are in place.
- Ensure the Quality of deliverables pre/post netlists (CLP, LEC, In-house tool checks).
- Close interactions with APR team to ensure that floorplanning/macro placements/quality of deliverables are in the right direction.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
