Principal Design Engineer

Micron Technology • San Jose, CA

2d • $181,000 - $361,000

About The Position

The Non-Volatile Engineering Group (NVEG) at Micron develops memory products that are best-in-class in die size, performance, reliability, and power! Our mission is to innovate and deliver groundbreaking non-volatile memory solutions such as NAND. As the pace of technology accelerates, NVEG is aggressively embedding AI across every stage of the design flow — from circuit exploration and layout optimization to silicon debug and specification analysis — and we are looking for engineers who not only use AI in their daily work but also actively reshape our engineering workflows to unlock AI’s full potential!

Requirements

• BS/MS/PhD in Electrical Engineering or a related field with 12+ years of high-speed IO or mixed-signal IC design experience, including leading IO architecture on multiple products.
• Deep expertise in high-speed transmitter and receiver design (drivers, receivers, serializer/deserializer, equalization) and source-synchronous timing.
• Strong background in clocking for IO: multi-phase clock generation, DCC/QEC, delay lines, and jitter and duty-cycle analysis.
• Experience closing IO timing and electrical specs across PVT, mismatch and aging, including impedance calibration and termination.
• Proven physical design teamwork: floorplanning, pad-ring planning, parasitic extraction and post-layout correlation.
• Silicon bring-up and debug experience, correlating silicon data with simulation.
• Daily hands-on use of AI tools in engineering work, with concrete examples where AI reduced design time or effort or improved design outcome.

Nice To Haves

• Experience with ONFI/Toggle NAND interfaces or DRAM interfaces (DDR4/5, LPDDR5/6, HBM3/3E/4).
• Channel and package co-design using IBIS/S-parameter models and statistical eye analysis.
• Low-power IO techniques: low-swing signaling, power gating, and fast wake-up.
• Sophisticated CMOS device physics, reliability mechanisms and BSIM modeling as they apply to high-speed IO.
• Building custom AI agents, LLM pipelines or ML models for IC design, verification, layout or silicon debug, and quantifying their impact.

Responsibilities

• Define, design and verify major IO blocks (output driver, pre-driver, serializer, slew-rate control, equalizers, input receiver, Vref generator, deserializer, clock distribution, multi-phase clock generation, DCC/QEC, calibration & training circuits) to meet ONFI/JEDEC timing and electrical specs
• Lead the IO timing budget (tDIVW, tDVW, setup/hold, jitter, duty-cycle distortion). Work with SI/PI engineers on channel, package and power-delivery effects (ISI, crosstalk, SSO noise, VCCQ ripple) and follow through between channel simulation and circuit design.
• Optimize IO power (ICCQ, energy per bit) and area. Drive floorplan, pad-ring and bump planning, clock routing and shielding with layout, and correlate post-layout results.
• Design for PVT, mismatch (Monte Carlo/high-sigma), aging (NBTI/HCI), ESD/latch-up and multi-die loading, with trims and margins that hold across the product lifetime.
• Plan characterization with product and test engineering, lead failure analysis of IO timing and electrical fails, and feed lessons back into the next design.
• Work with Applications Engineering and system teams to evaluate new interface specs and customer requests, and quantify feasibility and design trade-offs.
• Build efficiency by using AI daily. Incorporate AI into your work and adjust workflows. Summarize data from PVT, Monte Carlo, and post-layout SIM. Compose and maintain block-level and sub-system documentation to improve design efficiency continuously.
• Build agents, prompt libraries and scripts for recurring IO tasks, and restructure simulation setups and review checklists so AI can work on them.
• Pilot new tools and models, publish standard methodologies, and supervise measurable cycle-time and quality gains.
• Present to design reviews and expert panels, and mentor engineers on IO fundamentals and AI-first ways of working.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: Ph.D. or professional degree