Principal Design Engineer

Credo•San Jose, CA

13h•$180,000 - $250,000•Onsite

About The Position

Team Credo is looking for a Principal Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products. The ideal candidate possesses strong digital design fundamentals, hands-on RTL development experience, and a good understanding of high-speed SerDes architecture. This position will be onsite at our San Jose, CA HQ.

Requirements

BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
15+ years of digital design experience.
10+ years of block-level/system-level verification experience.
Proficient in bit-true verification and DPI/PLI verification methodology.
Strong RTL development skills using System Verilog.
Experience designing high-speed communication or DSP hardware.
Solid understanding of fixed-point arithmetic RTL implementation.
Experience with ASIC development flow (e.g. Lint, CDC/RDC, Synthesis, Timing analysis).
Familiarity with EDA tools from Synopsys, Cadence, or Siemens.
Strong debugging and problem-solving skills.

Nice To Haves

Experience in designing high-speed (>1GHz) SerDes chip.
Experience with low power design techniques, power estimation via post gate level simulation or other power analysis tools.
Familiarity with Forward Error Correction algorithms, including Reed-Solomon, BCH, LDPC, etc.
Familiarity with UVM verification methodology.

Responsibilities

Define RTL micro-architecture for digital PHY and SerDes DSP functions.
Develop synthesizable RTL for DSP blocks (FFE, DFE, MLSD, adaptive equalization, FEC, etc.).
Work with system architects and algorithm teams to translate DSP algorithms into RTL.
Optimize designs for performance, power, area, and latency.
Verify DSP modules and debug functional issues.
Support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
Analyze silicon bring-up data with validation teams to resolve issues.
Support PHY integration and system-level debugging.