Sr Layout Engineer, DDEG

Micron Technology • Boise, ID

23h

About The Position

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Layout Engineer in DDEG, you will translate schematics into manufacturable layouts that meet design intent, process rules, and schedule commitments for advanced DRAM. You’ll work closely with Design, Process Integration, and CAD teams to floorplan, implement, and verify custom digital, memory, and analog circuits – and help us continuously improve methods, automation, and documentation so others can follow. You will play a crucial role in developing layouts for critical custom, memory, analog, or standard cell circuits, ensuring predictable, on‑time delivery of memory designs.

Requirements

• Bachelor’s Degree or equivalent experience in Electrical/Computer Engineering (or related).
• Familiarity in layout tools and methodologies, including Cadence Virtuoso VXL and Calibre for DRC/LVS/Verifications.
• Exposure to semiconductor custom/memory/analog layout.
• Solid understanding of CMOS processes, design rules, and layout‑dependent effects.
• Proven problem‑solving in ambiguity with high attention to detail and quality.

Nice To Haves

• 3+ years of semiconductor custom/memory/analog layout experience with demonstrated block/project leadership, including mentoring and schedule management.
• DRAM/LPDDR/HBM memory product layout background
• Scripting (SKILL, Python) and experience building methodology/automation.
• Strong collaboration skills across global, multi-functional teams; excellent written documentation abilities.

Responsibilities

• Create layout designs for critical circuits, ensuring compliance with process rules and schematic intent.
• Work closely with Design, Process, and CAD engineers to deliver solutions from floorplan through final design.
• Perform verification tasks such as LVS (Layout vs. Schematic), DRC (Design Rule Check), and quality checks.
• Continuously improve verification tools and methodologies to ensure high‑quality layouts.
• Tackle ambiguous problems; prototype solutions without a playbook; then codify them into guides/SOPs and share with the team.
• Contribute scripts (e.g., SKILL/Python) and layout method improvements to advance automation and drive measurable productivity gains.
• Integrate automated layout solutions to shape the future of layout design.
• Coordinate with global partners to meet predictable schedules and support tapeout/mask generation processes.
• Deliver block‑level layouts within specified timelines while maintaining quality standards.
• Lead layout planning for assigned blocks or sub‑projects; coordinate priorities, provide guidance to other engineers, and ensure schedule alignment.
• Mentor team members on layout techniques, verification protocols, and tool usage.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees