The DRAM Design Engineering Group (DDEG) develops advanced memory solutions by tightly integrating design, layout, process integration, and CAD expertise. The team focuses on delivering high‑quality, manufacturable DRAM designs while continuously improving layout methods, automation, and documentation to support scalable and predictable execution. The Layout Engineer translates schematics and related geometry into manufacturable semiconductor layouts that meet design intent, process rules, and schedule commitments for advanced DRAM products. This role partners closely with Design, Process Integration, and CAD teams to floorplan, implement, verify, and deliver custom digital, memory, and analog layouts while contributing to methodology and automation improvements.
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Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees