Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX • Sunnyvale, CA

7d

About The Position

SpaceX is seeking a motivated, proactive, and intellectually curious engineer to work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

Requirements

• Bachelor's degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience in industry

Nice To Haves

• Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
• Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.)
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies
• Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
• Direct foundry DRM experience — able to read, interpret, and implement complex rule decks
• Experience at advanced nodes (4nm and below)
• Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
• Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

Responsibilities

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
• Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
• Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
• Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
• Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.
• Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

Benefits

• comprehensive medical, vision, and dental coverage
• access to a 401(k) retirement plan
• short & long-term disability insurance
• life insurance
• paid parental leave
• various other discounts and perks
• 3 weeks of paid vacation
• 10 or more paid holidays per year
• 5 days of sick leave per year (for exempt employees)

What This Job Offers

• Job Type: Full-time
• Career Level: Senior