Full-Chip Physical Design Verification Engineer

Tenstorrent•Fort Collins, CO

8d•$100,000 - $500,000•Hybrid

About The Position

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verification experience.
Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
Scripting proficiency in Python and TCL for automation and flow optimization.
Eligibility to access technology requiring a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

Nice To Haves

A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.

Responsibilities

Drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes.
Lead physical verification closure (DRC, LVS, ERC, etc.).
Debug issues using standard industry PV tools.
Collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts.
Mentor and technically lead in building efficient, manufacturable silicon.