Sr. Engineer, Process Development

Semtech•City of Industry, CA

1d•$95,000 - $135,000•Onsite

About The Position

The Process Engineer develops, optimizes, and sustains wafer fabrication processes supporting yield, quality, and throughput for InP photonic device lines, specifically InP Buried Heterostructure (BH) DFB lasers and BH Gain Chips (GC). The role owns one or more fab process modules, including photolithography, PECVD, dry etch, wet etch, and metallization. This includes Mesa etch and surface preparation steps that support MOCVD epitaxial regrowth of InP current-blocking layers used to form the buried heterostructure. The engineer applies technical training in materials, semiconductor processing, and statistical methods to resolve process excursions, improve device performance and yield, and transition processes into volume production. The position works with minimal supervision in a III-V cleanroom environment and partners with Wafer Fab Supervisors, Technicians, Equipment Engineering, Device and Test Engineering, and Quality to maintain Process-of-Record discipline, make data-based decisions, and support reliable, high-yield, high-volume manufacturing. The role may require flexibility to support engineering runs or excursions outside standard shift hours. The stated reasonable pay range is $95,000–$135,000. Base salary may depend on job-related qualifications, skills, education, experience, location, and other elements of total compensation.

Requirements

Master’s degree in materials science, electrical engineering, chemical engineering, physics, or a related engineering or science field.
2–5 years of experience in semiconductor or photonics wafer processing; relevant graduate research in III-V device fabrication may count toward experience.
Hands-on experience in one or more of photolithography, PECVD, dry etch, wet etch, and metallization.
Strong working knowledge of semiconductor process physics and chemistry, including lithography, thin-film deposition, plasma and wet etch, and metallization/ohmic contact formation for III-V materials.
Proficiency in statistical analysis, SPC, and DOE using JMP, Minitab, Python, or equivalent tools.
Ability to independently lead root-cause investigations and drive corrective actions to closure.
Ability to correlate process data with device electrical and optical performance.
Familiarity with fab metrology and characterization tools, including CD-SEM, profilometer, ellipsometer, XRD, SEM, and TLM test structures.
Strong written and verbal communication skills, including ability to present technical results to management and cross-functional teams.
Ability to work effectively with technicians, supervisors, and engineers in a team environment.
Ability to work in a cleanroom environment for extended periods across multiple process bays.
Ability to work around chemicals, including acids and solvents, process gases, and precious metals while following proper safety procedures.

Nice To Haves

Direct III-V/InP process experience.
Experience with InP-based laser or photonic integrated circuit fabrication.

Responsibilities

Own assigned process modules for InP BH DFB laser and BH GC production, with responsibility for process capability, stability, and yield performance.
Develop, characterize, and optimize lithography CD and overlay control, dielectric film properties, Mesa etch profile and depth control, surface preparation for MOCVD regrowth, and ohmic contact formation.
Define process windows, specifications, and control limits using designed experiments and statistical analysis.
Evaluate materials, chemistries, equipment, and process techniques to improve device performance, yield, throughput, and cost.
Characterize process results using SEM, profilometry, ellipsometry, TLM, and device electrical and optical test data; link process parameters to device performance.
Lead root-cause investigations and corrective actions for process excursions, yield loss, and drift.
Analyze in-line, wafer-level, and device-level data to identify yield detractors and prioritize improvement projects.
Use structured problem-solving methods, including 8D, fishbone, and FMEA, and short-loop experiments to isolate root causes and verify corrective actions.
Work with Equipment Engineering to resolve tool-related issues and qualify tools after maintenance or modification.
Define and review SPC charts, control limits, and monitoring strategies for assigned modules, and ensure out-of-control events are addressed in a timely manner.
Author and maintain POR documentation, process specifications, and work instructions for assigned process areas.
Approve and manage process changes through the change control system, including qualification and post-change verification of process stability.
Provide technical guidance, training, and process-specific direction to Wafer Fab Supervisors, Technicians, and Operators.
Plan and execute DOEs, process qualifications, and NPI process runs, and transition new or modified processes into volume production.
Partner with Device Engineering, MOCVD/Epitaxy, Test, Quality, and Production Planning to align process capability with product requirements and customer commitments.
Prepare technical reports, data summaries, and presentations for fab management and cross-functional teams.
Support customer and supplier technical reviews, audits, and failure analysis activities as needed.