SOC Platform Architect - IP Power

Qualcomm•San Diego, CA

1d•$140,000 - $210,000

About The Position

The infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW components such as Interconnect (NOC), System Cache, Memory controllers and System MMU that are implemented in all Qualcomm SoCs. This position primarily involves working with HW designer to gather power estimation of SOC Infra HW IPs, analyze the data, identify architectural and micro-architectural bugs/limitations and propose fixes and/or optimizations for the same. The ideal candidate should have a strong background in ASIC design and computer architecture while demonstrating good system level design/architecture understanding. The candidate will be required to co-ordinate with domain leads to ensure a robust infrastructure deployment plan based on product requirements. It requires understanding of HW architecture, HW-&-SW feature trade-off, and the complete silicon HW end-2-end design flow.

Requirements

Bachelor's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, or related work experience OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, architecture, or related work experience.
Robust understanding of computer architecture
Experience in system power architecture/design as well as exposure to power estimation flows.
Basic understanding of end-end ASIC design flows
Knowledge in SOC and Infrastructure IP (NOC, SMMU, Caches) HW architecture
Exposure to some form of interconnect protocol
Exposure to programming language for automation
Ability to quickly react and adapt to changes
Excellent communication skills
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

Exposure to Quality of Service, Clocks, Power management, Security and Debug architectures and their respective software interfaces
Good knowledge in industry standard Interconnect Protocol and IO Devices Protocol
Understanding of HW-SW interfaces and firmware
Experience in post-silicon flows and debugs

Responsibilities

Gather power estimation of SOC Infra HW IPs
Analyze power estimation data
Identify architectural and micro-architectural bugs/limitations
Propose fixes and/or optimizations
Coordinate with domain leads to ensure a robust infrastructure deployment plan based on product requirements