SoC Physical Design Formal Verification Engineer, HBM

Micron•Folsom, CA

16h

About The Position

As an SoC Physical Design Formal Verification Engineer in Micron Technology’s Heterogeneous Integration Group, you will own formal verification signoff for advanced HBM SoC logic/base die designs from RTL through synthesis, DFT insertion, place-and-route, ECOs, and tapeout. You will work with RTL design, physical design, DFT, low-power, and STA teams to ensure that implementation steps preserve functional and power intent. The role includes hands-on ownership of block and full-chip formal signoff and opportunities to shape formal methodology across product generations. You will also develop agentic AI flows using current LLM and generative AI capabilities. The position is full-time. The stated US base salary range is $124,000–$254,000 per year; additional compensation may include benefits, bonuses, and equity. Individual pay depends on location and job-related factors. Micron offers medical, dental, and vision plan choices; income-protection programs for illness or injury; paid family leave; paid time off; and paid holidays. The company describes its workplace as inclusive and emphasizes integrity, sustainability, community giving, personal wellbeing, and professional growth.

Requirements

Strong hands-on experience with formal equivalence checking on complex SoC designs at advanced process nodes.
Proficiency with industry formal verification tools, such as Cadence Conformal LEC/LP/ECO, Synopsys Formality/VC LP, Siemens Questa, or equivalent.
Solid understanding of the RTL-to-GDSII implementation flow, including synthesis, DFT insertion, placement, CTS, routing, and ECO flows, and how each step affects equivalence.
Experience debugging non-equivalence, aborts, and setup issues caused by synthesis optimizations such as retiming, register merging, clock gating, and multibit flops.
Working knowledge of UPF/CPF power intent and low-power concepts, including isolation, level shifting, retention, and power gating.
Familiarity with DFT structures such as scan, compression, MBIST, and JTAG, and their treatment in formal verification.
Good understanding of Verilog/SystemVerilog and gate-level netlists, with the ability to read and reason about RTL and synthesized logic.
Proven tapeout history on advanced foundries, such as TSMC, and understanding of full-cycle SoC development flows.
Strong scripting and automation skills using Python, TCL, Perl, and/or shell.
Ability to work in a global, cross-functional environment with strong communication and debugging skills.
Minimum 7 years of experience in a related field.

Nice To Haves

Experience with HBM, DRAM-adjacent, or memory-subsystem-heavy SoC designs.
Experience with functional ECO generation and implementation on large hierarchical designs.
Exposure to property-based formal verification (SVA or formal apps) or netlist-level CDC/RDC signoff.
Familiarity with physical verification and signoff concepts such as DRC, LVS, and STA.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Proven ability to mentor and develop junior engineers.

Responsibilities

Own formal equivalence checking (LEC) for HBM SoC blocks and full chip across RTL-to-netlist, post-synthesis, post-DFT, post-CTS, post-route, and ECO stages.
Develop and maintain equivalence setups that handle retiming, clock gating, multibit banking, constant or unreachable register optimization, scan and MBIST insertion, and black-boxed hard IP.
Debug non-equivalence and abort points, working with RTL, synthesis, DFT, and physical design teams to identify root causes and achieve clean signoff.
Perform static low-power verification against UPF power intent, including checks for isolation, level shifting, retention, power switches, and always-on connectivity through implementation.
Drive functional ECO generation and implementation with formal ECO tools while minimizing patch size and physical impact.
Run and review netlist-level structural and formal checks such as CDC/RDC, X-propagation, and connectivity checks as required for signoff.
Define formal verification signoff criteria, checklists, and QoR metrics, and represent formal status in tapeout readiness reviews.
Build and improve automated formal verification flows and regression infrastructure using Python, TCL, and shell.
Collaborate with EDA vendors to resolve tool issues, evaluate capabilities, and adopt methodology across product generations.
Develop agentic AI flows using current LLM and generative AI capabilities.
Mentor and develop junior engineers.