About The Position

The infrastructure IP Team consists of a multi-disciplinary group involved in the definition and design of SOC infrastructure HW components such as Interconnect (NOC), System Cache, Memory controllers, and System MMU that are implemented in all Qualcomm SoCs. This position primarily involves defining HW architecture for the next generation of SOC infrastructure HW IPs with ARM Architecture enabled and beyond. The ideal candidate should demonstrate the ability to define HW architectures based on Product Requirements and HW-SW interfaces that are SW developer friendly. It requires deep understanding of HW architecture, HW-&-SW feature trade-off, and the complete silicon HW end-2-end design flow. This is a challenging position, defining and driving our most innovative technologies.

Requirements

  • Strong knowledge and hands-on experience with multi-die / chiplet architectures and Die-to-Die, Chip-to-Chip Links.
  • Strong knowledge in industry standard Interconnect Protocol and IO Devices Protocol
  • Strong knowledge in SOC and Infrastructure IP (NOC, SMMU, Caches) HW architecture
  • Strong knowledge in Quality of Service, Clocks, Power management, Security and Debug architectures and their respective software interfaces
  • Good knowledge in HW-SW interfaces and firmware
  • Experience with Performance modeling and validation
  • Experience with RTL design and complete design flow
  • Ability to quickly react and adapt to changes.
  • Excellent communication skills.
  • Bachelor's degree in Electrical Engineering, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
  • OR Master's degree in Electrical Engineering, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.
  • OR PhD in Electrical Engineering, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.
  • 2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).

Nice To Haves

  • Strong knowledge in SOC infrastructure IP (NOC, Caches, SMMU, Memory Controller, Interrupt Handler)
  • Strong knowledge in Platform System Architecture (example : ARM or X86 or RISC-V )
  • Strong experience with industry standards (PCIe, CXL, USB, UFS, MIPI, UCIe,…)
  • Strong knowledge in ARM Advanced Technology in the area of Security, RAS, MPAM, Memory Tagging, etc.
  • Strong knowledge in HW-SW interfaces, APIs & firmware
  • Experience in Data Science, Machine Learning is a plus
  • Experience in Functional Safety is a plus

Responsibilities

  • Defining HW architecture for the next generation of SOC infrastructure HW IPs with ARM Architecture enabled and beyond.
  • Defining HW architectures based on Product Requirements and HW-SW interfaces that are SW developer friendly.
  • Driving innovative technologies.

Benefits

  • competitive annual discretionary bonus program
  • opportunity for annual RSU grants
  • highly competitive benefits package
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