Silicon Validation Lead, Principal Engineer - 19499

Synopsys•Sunnyvale, CA
•$193,200 - $289,800•Onsite

About The Position

Synopsys is seeking an accomplished engineer to lead silicon validation of high-speed serial communication IP. The role bridges simulation and silicon, validating functionality and performance against architectural intent and ensuring robust results across complex systems. It includes hands-on hardware bring-up, firmware integration, early product characterization, and resolution of silicon issues. The engineer will validate sim-to-silicon performance for algorithms, impairments, and key metrics; guide system teams on hardware-correlated models and tuning; and improve SerDes algorithms and configurations to address performance gaps. The role also incorporates customer evaluation-board learnings, reviews firmware regression tests, supports customer bring-up, and communicates findings to Platform Architects and Product Owners. The position is part of Synopsys’ Enterprise SerDes R&D team, collaborating with analog, digital, and hardware engineering experts on next-generation connectivity solutions. The role is based in Sunnyvale, California, and is not remote eligible.

Requirements

  • BSc or MSc in Electrical or Computer Engineering.
  • 10 or more years of experience in silicon validation, high-speed interfaces, and system-level performance analysis.
  • Expertise in SerDes design and validation, including PCIe and Ethernet protocols.
  • Strong knowledge of signal integrity, equalization, coding, and CDR architectures.
  • Hands-on experience with lab validation, debug tools, and sim-to-silicon correlation.
  • Familiarity with firmware integration and regression testing methodologies.
  • Innovative, detail-oriented, and results-driven.
  • Strong communication and collaboration skills across multidisciplinary teams.
  • Adaptable and customer-focused, with a passion for solving complex technical challenges.

Responsibilities

  • Lead silicon validation of IP functionality and performance, ensuring alignment with architectural intent.
  • Support hardware bring-up and firmware integration for early product-version characterization.
  • Drive root-cause analysis, workarounds, and fixes for issues uncovered during characterization.
  • Manage a dedicated validation effort in parallel with characterization activities.
  • Validate sim-to-silicon performance of algorithms, impairments, and key metrics such as AFE curves.
  • Provide feedback to system teams on hardware-correlated models and performance tuning.
  • Develop improvements to SerDes algorithms and configurations to address performance gaps.
  • Incorporate learnings from customer evaluation boards into future developments.
  • Review firmware regression tests for repeatability, drift, and robustness.
  • Support customer bring-up and drive resolution of silicon debug issues.
  • Communicate findings to Platform Architects and Product Owners for continuous platform improvement.

Benefits

  • May be eligible for an annual bonus, equity, and other discretionary bonuses.
  • Comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.
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