Silicon Technical Program Manager

Normal Computing Corporation•Palo Alto, CA

About The Position

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry, critical AI infrastructure, and broader systems. The Silicon Technical Program Manager partners with engineering leads to turn company objectives into actionable milestones across the engineering organization and owns the schedule throughout the silicon development lifecycle. The role coordinates work across internationally distributed teams, tracks progress, identifies and mitigates risks, resolves cross-team issues, and provides engineering executives with clear, digestible project updates to help ensure on-time delivery.

Requirements

  • 10+ years of experience in semiconductor development.
  • 3+ years as a TPM or program lead on complex ASIC or SoC architectures.
  • Excellent communication and stakeholder management skills, including the ability to influence without authority.
  • Experience at companies with complex software/hardware integration.
  • Proven track record managing internationally distributed engineering teams.
  • Proficiency with program management tools such as Jira, Asana, or Linear.
  • Experience with every element of the silicon lifecycle, from architecture and RTL generation through verification, tapeout, bring-up, and post-silicon validation.
  • Ability to think out of the box to find solutions.

Nice To Haves

  • Ph.D. in an electrical engineering discipline.
  • Familiarity with chiplets and 3D packaging.
  • Expertise using Linear for program management tracking.
  • Familiarity with heterogeneous systems used for AI inference.
  • Experience working with external silicon foundries, Tier II vendors, and OSAT vendors.
  • Experience working at a silicon startup.

Responsibilities

  • Break down company objectives into actionable milestones across the engineering organization.
  • Own the schedule across the silicon development lifecycle, including architecture, micro-architecture, RTL generation, verification, logic synthesis, design for test, physical design, physical verification, tapeout, packaging, post-silicon testing, bring-up, and post-silicon validation.
  • Coordinate silicon development efforts across teams in Mountain View, New York, London, Zurich, and Copenhagen.
  • Define metrics and create dashboards or other mechanisms to surface information and track progress.
  • Identify and mitigate risks to delivery schedules and quality.
  • Synthesize complex technical status, trade-offs, and risks into clear updates for executive leadership.
  • Help resolve issues across teams.
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