Silicon IP Verification Methodology Lead

Ericsson•Austin, TX

2d•Hybrid

About The Position

Ericsson Silicon is seeking a seasoned Silicon IP/Verification Methodology Lead to join their dynamic team within the newly established Frontend CAD department. This role is dedicated to defining methodologies and EDA workflows across global R&D sites. The lead will play a critical role in shaping and executing the verification methodology for ASIC IP and SoC development, leveraging extensive experience to drive efficiency, ensure quality, and implement best practices across verification processes.

Requirements

Deep expertise in ASIC IP/ASIC SoC design, RTL, Verilog, and System Verilog.
Proficiency in front-end tools including Verilog simulators, linters, clock domain crossing checkers.
Familiarity with synthesis, static timing analysis, Design-For-Test (DFT).
Proficiency in scripting languages such as Perl and Python.
Extensive understanding of modern design methodologies and techniques.
Experience in coordinating and supporting geographically dispersed engineering teams.
Strong communication and presentation skills.
Self-driven with the ability to manage engineering loads across multiple teams.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
15+ years of experience in IP/SoC verification, with a proven track record of successful project deliveries.
Deep understanding of verification methodologies, including UVM, OVM, and formal verification techniques.
Extensive experience with verification tools such as VCS and Xcelium.
Strong programming skills in SystemVerilog, Verilog, and scripting languages (e.g., Python).
Excellent problem-solving skills and the ability to analyze and resolve complex verification issues.
Proven leadership abilities, with experience managing and mentoring verification teams.
Strong communication skills, with the ability to effectively collaborate with cross-functional teams.
A proactive and innovative mindset, with a passion for driving continuous improvement.

Nice To Haves

Knowledge of System-Verilog assertions, checkers, and advanced design verification techniques is advantageous.

Responsibilities

Lead the development and implementation of advanced verification methodologies for ASIC IP and SoC projects.
Oversee the verification lifecycle, from planning and testbench development to execution and closure.
Collaborate with cross-functional teams to define verification requirements and ensure alignment with overall project goals.
Drive the adoption of cutting-edge verification tools and technologies to improve productivity and quality.
Mentor and guide junior verification engineers, fostering a culture of continuous learning and improvement.
Analyze and resolve complex verification issues, ensuring timely delivery of high-quality IP and SoC designs.
Maintain up-to-date knowledge of industry trends and advancements in verification techniques and methodologies.
Develop and implement metrics to measure and improve verification effectiveness and efficiency.
Work closely with the design and architecture teams to identify potential verification challenges and develop strategies to address them.

Benefits

Choice of three medical plan options
Dental plan option
Company credits towards medical and dental premiums
401(k) Plan with automatic 3% company contribution
401(k) matching $1 for $1 on the first 3% of eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay
Company credits for basic life insurance and basic accidental death and dismemberment coverage
Company credits for short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time
80 hours of sick time annually
Up to 16 weeks of paid maternity leave
6 weeks of parental or adoption leave at 100% of pay
Financial wellness programs
Educational assistance
Matching gifts
Recognition programs