Silicon Engineering Manager, EMIR and Power Grid, AI/ML

Google•Sunnyvale, CA

6d•$192,000 - $278,000

About The Position

In this role, you will help shape AI/ML hardware acceleration by driving Tensor Processing Unit (TPU) technology for demanding AI/ML applications. You will manage a team working with physical design, circuits, technology, and package leads to develop ASICs and SoCs for advanced technology nodes. The role focuses on optimizing, analyzing, customizing, and verifying power delivery networks to meet performance and integrity specifications. You will manage technical evaluations of EDA tools, process nodes, and IPs, and recommend solutions. You will develop power delivery and reliability solutions and methodologies that co-optimize across the design space, taking them from inception through maturity and tapeout. The role also involves establishing EMIR budgets and signoff methodologies, coordinating analysis and signoff, and developing the team. The AI and Infrastructure team delivers AI and infrastructure capabilities at scale for Google customers, Googlers, and Google users worldwide.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of technical experience in physical design disciplines involving power delivery and advanced process technology nodes.
3 years of experience in people management and developing employees.
Experience with power grid integrity (EMIR) from initial budgeting through analysis, verification, and final signoff.
Experience using standard EMIR tools such as RedHawk, Totem, and Voltus; establishing EMIR budgets; defining signoff methodologies; and bringing up flows for new projects.
Experience with power grid design and related design trade-offs.

Nice To Haves

Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience owning EMIR at the block or full-chip level, including proactive floorplanning and defining standard cell usage with physical design owners.
Experience with power delivery voltage droop mitigation.
Knowledge of the semiconductor project life cycle and quality goals across functions.
Familiarity with low-power design techniques such as multi-Vth, power/voltage domain design, clock gating, power gating, and Dynamic Voltage Frequency Scaling.

Responsibilities

Direct, manage, and set strategy for the power grid distribution and power integrity team, identifying required skills and allocating resources across active projects.
Manage the EMIR team’s analysis at block, sub-chip, and full-chip levels, and execute comprehensive signoff checks to ensure final design reliability.
Collaborate with physical design, STA, package, and circuit teams to define EMIR budgets, signoff methodologies, and proactive mitigation strategies, including optimal floorplanning and standard cell selection.
Work with internal groups and external software vendors to establish priorities and define critical capabilities for EMIR tools.
Create customized development plans, manage staffing initiatives, and foster a collaborative environment to maximize team members’ impact and productivity.
Manage technical evaluations of EDA tools, process nodes, and IPs, and provide recommendations.
Develop power delivery and reliability solutions and methodologies, carrying them from inception through maturity and tapeout.