Silicon Design Verification Manager

Google•Austin, TX

4d•$192,000 - $278,000•Hybrid

About The Position

The US base salary range for this full-time position is $192,000 - $278,000 + 20% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google [https://www.google.com/about/careers/applications/benefits/]. Position reports to the Google Austin, TX office & may allow for a hybrid schedule per Google policy. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 10 years of progressive, post-baccalaureate experience in the job offered or in a Silicon Design Verification-related occupation.
Alternatively, will accept a Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field, and 8 years of experience in the job offered or in a Silicon Design Verification-related occupation.
Position requires 8 years of experience in the following: Developing and guiding teams in advanced verification methodologies; Processor Architecture including multi-processor cache coherency; Object Oriented design verification coding (System Verilog or C++); Testbench architecture design using agents, stimulus, checkers, and scoreboards; and Simulation-based verification at block and integration levels.

Responsibilities

Lead a medium-sized team by setting clear priorities and conducting regular meetings to drive individual performance and career development.
Develop comprehensive test plans that outline verification strategies, environments, components, stimulus, and coverage while maintaining clear documentation.
Apply advanced verification methodologies and languages like SystemVerilog to validate the functional correctness of complex IP-level designs.
Collaborate closely with architecture and design teams to ensure logical correctness and alignment across cross-functional specifications.
Debug design failures and verify functional integrity by utilizing standard verification techniques and rigorous failure analysis. Oversee the lifecycle of IP-level complexity projects to ensure all verification objectives support organizational goals and timelines.