Silicon Design Engineer

Advanced Micro Devices, Inc•San Jose, CA

About The Position

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: We are seeking a highly motivated Silicon Design Engineer with strong RTL-to-GDS background and full ASIC design flow experience to join AMD's AECG Silicon Integration & Test team. This role focuses on design and verification of advanced silicon testchips, including place-and-route, timing closure, physical verification, design signoff, and tapeout readiness. The successful candidate will work closely with front-end design, CAD, and silicon validation teams to deliver leading-edge FPGA and ASIC testchip solutions.

Requirements

Expertise in digital ASIC/SoC implementation flows, including synthesis, floorplanning, power planning, placement, CTS, routing, timing closure, and physical signoff using industry-standard tools (Cadence Genus/Innovus and/or Synopsys Fusion Compiler).
Strong understanding of CMOS circuit design fundamentals, semiconductor device physics, signal integrity, power integrity, and device reliability mechanisms.
Proven experience delivering silicon across advanced process technologies, including FinFET (7nm/5nm/3nm) and emerging Gate-All-Around (GAA) nodes.
Hands-on experience with physical signoff methodologies, including STA, IR drop, electromigration (EM), DRC/LVS, noise analysis, and tapeout qualification.
Strong analytical and problem-solving skills, with experience debugging complex design implementation issues and driving cross-functional closure.
Proficiency in Python, Tcl, and shell scripting for automation, flow development, and productivity enhancement.

Nice To Haves

Experience in small, fast-moving environments where engineers take broad ownership is highly valued.
Experience with silicon bring-up, post-silicon validation, and laboratory test equipment is a plus.

Responsibilities

Drive the timing-aware/physical-aware synthesis flow using industry-standard tools (e.g., Design Compiler) to generate optimized netlists.
Lead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, signal integrity optimization, physical verification, and design signoff.
Close SoC timing with Static Timing Analysis (STA) using tools such as PrimeTime to validate setup/hold margins across process, voltage, and temperature (PVT) corners.
Drive tapeout readiness by performing physical signoff analyses including IR drop, electromigration (EM), noise, DRC/LVS verification, and cross-functional reviews with RTL, DFT, package, and foundry teams.
Assist with post‑silicon bring-up, debugging, and lab‑based validation activities.