Signoff Static Timing Analysis and Spice CAD Engineer
About The Position
Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of Signoff solutions for the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define and develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge internal and EDA technologies in the Signoff domain, including pioneering in genAI/ML, and developing good-by-construction hierarchical solution, as well as enabling the latest STA features to reduce conservatism in Signoff.
Requirements
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Signoff Timing and spice simulation experience
- CAD development skills
- Scripting tools and programming languages: Python and TCL preferred.
Nice To Haves
- Bachelor’s degree, Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field.
- Maths minor is a plus.
- Deep knowledge of STA features and Timing concepts.
- 2-6 years of experience in Signoff Timing of SoCs at either top-level or block-level.
- 2-6 years of experience with scripting tools and programming languages: Python and TCL preferred.
Responsibilities
- Improving the Timing and Cell Characterization methodology for diverse Mobile, Compute, AI, IoT Snapdragon chips.
- Participate in the enablement and validation of new cell characterization methodologies and features, through careful spice correlation and CAD development.
- Collaborate with AI team on ground-breaking initiatives for compute and turn-around time reduction.
- Correlation of STA tools with spice, version-to-version validation.
- Provide solutions to the Snapdragon design teams, analyze their requests, and address their requests through ticket queues.
- Interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirement.
- Setting up, augmenting, and maintaining a regression of complex STA designs
- Participate to the STA and Cell Characterization flows and features enablement for foundry advanced process nodes, at block, subsystem, and top level.
- Participate to the enablement of new methodologies and features for turn-around time reduction on various subsystems such as Modem, GPU, CPU, DDR, Camera, Video, NSP.
- Interface and drive EDA vendor Application Engineers on the resolution of Signoff problems faced by the Snapdragon design teams.
- Participate to the specification of new Signoff CAD solutions addressing the PPA requirements of the design teams.
- Deep dive on STA or/and spice issues and establish as a go-to domain expert.
- Participate along with Qualcomm talented AI team to R&D initiatives driving differentiation in terms of compute and turn-around time.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
