Static Timing Analysis (STA) Engineer

Altera•Toronto, ON

2d•CA$102,900 - CA$149,100•Onsite

About The Position

Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross-functional teams to deliver high-performance, power-efficient designs. The ideal candidate has a strong foundation in STA, experience with modern design flows, and the ability to work effectively in a collaborative engineering environment.

Requirements

6+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs.
Solid understanding of STA fundamentals (setup/hold, timing paths, clocking, CDC basics)
Experience with industry-standard tools (e.g., PrimeTime or equivalent)
Familiarity with synthesis and place & route flows
Working knowledge of: RTL design (Verilog/SystemVerilog)
Working knowledge of FPGA or ASIC design methodologies
Ability to analyze timing reports, identify root causes, and propose actionable solutions.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Applicants must be eligible for any required Canada export authorizations.

Nice To Haves

Experience with FPGA architectures and timing flows
Familiarity with advanced process nodes or high-speed designs
Scripting experience (e.g., Tcl, Python) for automation
Exposure to large-scale or distributed engineering environments

Responsibilities

Perform static timing analysis for FPGA designs, including setup/hold checks, constraint validation, and timing signoff support.
Identify, debug, and resolve timing violations in collaboration with RTL, synthesis, and physical design teams.
Assist in developing and validating timing constraints to ensure accurate modeling of design intent.
Work closely with design, architecture, and implementation teams to improve timing convergence.
Apply established STA methodologies and contribute to flow improvements and automation where applicable.
Support optimization efforts for performance, power, and area (PPA) through timing-driven analysis.