Manager, Static Timing Analysis (STA)

Altera•Toronto, ON

2d•CA$144,600 - CA$209,300•Onsite

About The Position

Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs. This role will play a critical part in ensuring high-performance, power-efficient silicon by driving timing methodology, analysis, and optimization across complex designs. The ideal candidate brings deep STA expertise, strong leadership experience, and a proven ability to collaborate across design, physical implementation, and architecture teams.

Requirements

10+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs.
3+ years of experience managing or leading engineering teams.
Deep knowledge of STA concepts (setup/hold, clock domain crossing, timing constraints)
Strong experience with timing signoff tools (e.g., PrimeTime or equivalent)
Understanding of synthesis, place & route, and full chip implementation flows
Solid understanding of RTL design (Verilog/SystemVerilog)
Solid understanding of Timing closure methodologies
Solid understanding of Low-power and high-performance design challenges
Strong skills in root-cause analysis of timing violations and driving closure across complex designs.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Nice To Haves

Experience with FPGA architecture and design flows
Familiarity with advanced nodes and high-speed designs
Exposure to scripting/automation (e.g., Tcl, Python) for timing analysis
Experience working in large-scale, distributed engineering environments

Responsibilities

Team Leadership: Build, manage, and mentor a high-performing STA team; drive technical excellence and career development.
Timing Closure & Signoff: Own end-to-end STA for FPGA designs, including constraint development, timing analysis, and timing signoff.
Methodology Development: Define and implement robust STA methodologies, flows, and best practices to improve timing convergence and design quality.
Cross-Functional Collaboration: Partner with RTL design, synthesis, physical design (P&R), and architecture teams to identify and resolve timing issues.
Performance Optimization: Drive improvements in performance, power, and area (PPA) through timing-driven design and optimization techniques.
Tool & Flow Expertise: Leverage industry-standard EDA tools to analyze timing, debug violations, and automate flows where applicable.
Project Execution: Ensure on-time delivery of timing closure milestones across multiple programs.