Senior VLSI CAD Engineer

NVIDIA•Austin, TX

1d•Hybrid

About The Position

Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to power the next generation of AI and accelerated computing. Our team operates at the intersection of cutting-edge circuit design and scalable CAD infrastructure, tackling some of the most complex memory design challenges in the industry. As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows that enable our designers to move faster and innovate further. Unlike typical CAD roles, this position offers direct impact on a dynamic chip roadmap—your infrastructure work will directly shape the silicon that drives NVIDIA's most advanced products. You will collaborate with world-class circuit design, layout, and technology teams across geographies, as well as engage directly with leading EDA vendors to drive tooling that meets our unique requirements. If you are a passionate engineer who thrives at the frontier of EDA tool development and loves solving hard scalability challenges, this is the team for you.

Requirements

MS in Computer Science/Engineering, Electrical Engineering or equivalent experience.
Minimum of 5+ years of CAD flow developments and design methodology in VLSI.
Good programming skills in multiple languages (Bash, TCL, Python, Perl, Makefile).
Prior experience with development, testing and deployment of EDA tools.
Self-starter with passion for growth, real enthusiasm for continuous learning and sharing findings across the team.

Nice To Haves

Experience working with industry standard EDA tools like HSPICE, PrimeSim-XA, ESP, NanoTime/PrimeTime, Totem/SeaHawk .
Knowledge of DC/Transient, Cross corner PVT and Monte Carlo simulations.
Previous work in VLSI, ASIC, or EDA is a definite plus.
Ability to use the latest AI tools to improve design productivity.
Experience in evaluating CAD products and driving EDA vendors to meet the team’s requirements.

Responsibilities

Build flows and methodology around vendor EDA tools to streamline circuit design and verification workflows.
Bring up compiler workspaces for new projects and ensure all internal flows, infrastructure, and tools are in sync across a multi-project development environment.
Develop and maintain regression suites to validate design quality before releases; optimize regression infrastructure to balance thoroughness with turnaround time, enabling circuit designers to iterate with agility.
Own and manage the release process for custom RAM circuit macros delivered to Place-and-Route (PNR) teams — including gatekeeping all collateral, coordinating with management on release schedules, and ensuring both internal and external customer teams are ready for each release.
Ensure seamless integration of RAM compilers into PNR flows across NVIDIA — understand how compilers are used downstream, triage and resolve bugs related to RAM compiler builds.
Maintain versioned records of tool and infrastructure for each design release.
Own the web front-end that circuit designers use to access simulation data and interact with design collateral — ensure data is presented clearly to support sound design decisions and streamline design reviews.
Collaborate with circuit design, layout, technology, and 3rd party EDA vendor teams distributed across geographies and time zones.