Senior Verification Engineer – High Speed Coherent Interconnect Hub

NVIDIA•Us, CA

3d•Hybrid

About The Position

NVIDIA is seeking a motivated and creative Senior Verification Engineer to join its Tegra SoC IP Verification team. The team builds IP for next-generation scalable, high-performance, multi-chip computing platforms. The engineer will work closely with architecture and design teams to verify complex High Speed Coherent Interconnect Hub IP, define verification strategies, develop robust verification environments, drive functional and performance verification, close coverage, and ensure high-quality design signoff. The position supports technologies at the heart of NVIDIA's next-generation computing platforms.

Requirements

BS, MS, or equivalent experience.
At least 3 years of ASIC verification experience with complex IPs or SoC subsystems.
Strong background in SystemVerilog, UVM, constrained-random verification, and coverage-driven verification methodologies.
Experience developing verification environments, checkers, assertions, and functional coverage.
Strong debugging and problem-solving skills, with experience using industry-standard simulation and debug tools.

Nice To Haves

Experience verifying high-speed coherent interconnects, NoCs, or other complex SoC infrastructure IP.
Knowledge of coherent interconnect protocols and technologies such as CHI and AXI.
Strong understanding of cache coherency, transaction ordering, and system-level data flows.
Experience with performance verification, including bandwidth, latency, QoS, and traffic management.
Strong scripting skills in Python, Perl, or Shell.
Excellent communication and collaboration skills.

Responsibilities

Develop and maintain verification infrastructure, including testbenches, BFMs, checkers, monitors, scoreboards, assertions, and constrained-random stimulus.
Define, review, and complete verification test plans for coherency protocol, ordering, error handling, performance, and other key IP features.
Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces.
Develop and complete performance test plans to validate bandwidth, latency, QoS, and other performance requirements.
Drive functional and code coverage closure and provide verification signoff.
Debug complex RTL and verification issues and work with architecture and design teams to resolve them.
Collaborate with FPGA, emulation, software, and post-silicon teams to support system validation and silicon bring-up.