Senior Technology Engineer
Lattice Semiconductor•San Jose, CA
•$211,200
About The Position
Responsible for the interface between Lattice engineering and external foundries to enable successful process adoption and on-time tape-out. Ensure PDK readiness, and ensure alignment between internal EDA, design teams, and foundry requirements.
Requirements
- BS/MS/PhD in Electrical Engineering or related field
- 10+ years in semiconductor technology and foundry interfacing roles
- Deep understanding of advanced process nodes and device physics
- Proven ability to work with external partners (foundry, EDA, and IP vendors)
- Strong cross-functional collaboration and communication skills
Nice To Haves
- Direct experience with TSMC and Samsung foundry ecosystems
- Strong understanding of CAD/EDA flows (PDK, reliability, ESD, EM/IR, SI/PI, etc.)
- Experience supporting tape-out and silicon validation across multiple nodes
Responsibilities
- Serve as the primary technical interface to foundries, driving technical alignment, issue resolution, and escalations
- Partner with EDA teams on procurement, validation, and rollout of PDKs, models, and technology collateral
- Ensure design and signoff flows align with foundry requirements (DRC/LVS, EM/IR, ESD, SI/PI, reliability, etc.)
- Own device test structure definition and support silicon characterization to validate process assumptions
- Establish and scale processes for managing technology collateral, documentation, and design methodology consistency across programs
Benefits
- healthcare and retirement plans
- paid time off
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What This Job Offers
Job Type
Full-time
Career Level
Senior
