Senior System Level Verification Engineer

Axiado • San Jose, CA

8h • Onsite

About The Position

The Design Verification Technical Team Lead position is an opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IOT. You will be responsible for chip level verification of complex ARM based SOC HW, debugging, and ROM and FW bringup.

Requirements

• 7 years of DV or validation experience
• 5 years of system Level verification experience using C
• Has worked through complete project cycle of an SOC ASIC chip
• Thorough understanding of CPU and its debug architecture, as well as SOC system architecture
• Proficient in programming and modeling typical SOC connected devices, such as JTAG, UART, SPI, I2C.
• Proficient in testplanning, test case development using C, and self checking in such tests
• Proficient in RTL debugging using waveform viewer
• Mastery in C programming
• Fluent in scripting languages such as Make, Python, Perl and shell script
• Fluent in documentation and issue tracking using Confluence and Jira tools

Nice To Haves

• Validation on emulation, FPGA and post-silicon
• Complex IP interface validation of USB, Ethernet, PCIE, DDR
• Using AI tools in testplanning, generation and debugging

Responsibilities

• Develop SOC system level test environment for simulation and emulation, including log generation, backdoor configuration and device modeling
• Develop testplan and tests, including error condition tests and stress tests
• Run and debug tests in regressions, both in simulation and on emulator
• Work with other teams in root-causing HW issues, and creating system level test cases for them
• Validation ROM
• Work with SW team in debugging device driver issues, and OS boots

What This Job Offers

• Job Type: Full-time
• Career Level: Senior