Senior Synthesis Engineer

Qualcomm•Austin, TX

5d•$115,600 - $173,400

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Requirements

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Minimum 0 to 6 years of hands on experience in Synthesis and LEC

Nice To Haves

Proficiency in Python/Tcl
Familiar with Synthesis tools (Fusion Compiler/Genus)
Fair knowledge in LEC, LP signoff tools
Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus

Responsibilities

Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
Experience in all aspects of timing closure for multi-clock domain designs.
Should be familiar with MCMM synthesis and optimization.
Should have good understanding of low-power design implementation using UPF.
Experience with scripting language such as Perl/ Python, TCL.
Experience with different power optimization flows or technique such as clock gating.
Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation
Should be able to handle ECOs and formal verification and maintain high quality matrix