High-Level Synthesis (HLS) Engineer

Altera Semiconductor•San Jose, CA

4d•Onsite

About The Position

Altera is seeking a High-Level Synthesis (HLS) Engineer to join their cutting-edge compiler systems team. This role involves bridging the gap between software and hardware by transforming high-level programming models into highly optimized hardware implementations. The HLS team focuses on enabling breakthroughs in AI, cloud infrastructure, and domain-specific acceleration. The ideal candidate will be excited about pushing the boundaries of compilers, systems, and hardware/software co-design.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
3+ years of experience.
Strong foundation in one or more of the following: Compiler design (e.g., optimization, IR design, code generation), Programming languages or systems, Computer architecture or digital design.
Proficiency in C/C++ or similar systems programming languages.
Applicants must be eligible for any required U.S. export authorizations.

Nice To Haves

Research experience in compilers, HLS, or hardware/software co-design.
Familiarity with LLVM, MLIR, or similar compiler infrastructures.
Exposure to FPGA/ASIC design flows or hardware description languages (Verilog/VHDL).
Background in optimizing AI/ML workloads or domain-specific accelerators.
Publications in relevant conferences or demonstrated research impact.

Responsibilities

Design and develop next-generation compiler infrastructure for HLS.
Invent and implement novel compiler passes, optimizations, and code transformations for hardware synthesis.
Explore advanced compilation techniques for AI/ML workloads, including graph-level and system-level optimizations.
Improve end-to-end compilation flow from C/C++ (and beyond) to RTL, focusing on performance, power, and area efficiency.
Prototype and evaluate new ideas in collaboration with research and product teams.
Contribute to publications, patents, and internal technical innovations.
Work closely with hardware architects and domain experts to co-design future acceleration platforms.