High-Level Synthesis (HLS) Engineer

Altera•San Jose, CA

1d•$133,200 - $192,800•Onsite

About The Position

Altera is seeking a High-Level Synthesis (HLS) Engineer to join their cutting-edge compiler systems team. This role involves transforming high-level programming models into optimized hardware implementations for FPGAs, contributing to breakthroughs in AI, cloud infrastructure, and domain-specific acceleration. The engineer will work on both production compiler systems and forward-looking research, focusing on designing and developing next-generation compiler infrastructure, inventing novel compiler passes and optimizations, and exploring advanced compilation techniques for AI/ML workloads. The position requires improving the end-to-end compilation flow from C/C++ to RTL, with an emphasis on performance, power, and area efficiency. Collaboration with research and product teams, as well as hardware architects and domain experts, is expected. The role also involves contributing to publications, patents, and internal technical innovations.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field
3+ years of experience
Strong foundation in one or more of the following: Compiler design (e.g., optimization, IR design, code generation), Programming languages or systems, Computer architecture or digital design
Proficiency in C/C++ or similar systems programming languages

Nice To Haves

Research experience in compilers, HLS, or hardware/software co-design
Familiarity with LLVM, MLIR, or similar compiler infrastructures
Exposure to FPGA/ASIC design flows or hardware description languages (Verilog/VHDL)
Background in optimizing AI/ML workloads or domain-specific accelerators
Publications in relevant conferences or demonstrated research impact

Responsibilities

Design and develop next-generation compiler infrastructure for HLS
Invent and implement novel compiler passes, optimizations, and code transformations for hardware synthesis
Explore advanced compilation techniques for AI/ML workloads, including graph-level and system-level optimizations
Improve end-to-end compilation flow from C/C++ (and beyond) to RTL, focusing on performance, power, and area efficiency
Prototype and evaluate new ideas in collaboration with research and product teams
Contribute to publications, patents, and internal technical innovations
Work closely with hardware architects and domain experts to co-design future acceleration platforms