Senior Staff Verification Engineer - PCIe & Memory Subsystems
About The Position
In this role, you will architect and develop a functional verification environment, including reference models and bus-functional monitors and drivers, and contribute to the methodology behind such development. Activities may include: Writing a verification test plan that employs random techniques, directed testing, and coverage analysis to thoroughly check functional correctness and performance. Developing a testbench using UVM, System Verilog, C/C++, and DPI. Verification at different levels of hierarchy, including block/unit, subsystem, and SOC levels. Working closely with logic designers to ensure the test plan is complete, debug simulation failures, and resolve issues. Expertise in PCIe and Memory Subsystems is highly desirable.
Requirements
- BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering
- 5-10 years of relevant professional experience.
- Background in creating test plans and designing test bench architectures that are hierarchical, reusable, and scalable.
- Background in SOC verification and test bench development using UVM and System Verilog, object-oriented programming, and constrained random methods.
- Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems.
- Effective communication and teamwork skills
- Mindset for high quality and attention to detail
- Independent learner, proactive in problem-solving and finding solutions
Nice To Haves
- Expertise in PCIe and Memory Subsystems
Responsibilities
- Architect and develop a functional verification environment, including reference models and bus-functional monitors and drivers.
- Contribute to the methodology behind such development.
- Write a verification test plan that employs random techniques, directed testing, and coverage analysis to thoroughly check functional correctness and performance.
- Develop a testbench using UVM, System Verilog, C/C++, and DPI.
- Perform verification at different levels of hierarchy, including block/unit, subsystem, and SOC levels.
- Work closely with logic designers to ensure the test plan is complete, debug simulation failures, and resolve issues.
Benefits
- Employee stock purchase plan with a 2-year look back
- Family support programs
- Robust mental health resources
- Recognition and service awards
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What This Job Offers
Job Type
Full-time
Career Level
Senior
