Senior Staff RTL Verification Engineer

Impinj•Seattle, WA

1d•$158,700 - $238,100•Remote

About The Position

Impinj is a leading RAIN RFID provider and Internet of Things pioneer. We’re inventing ways to connect every thing to the Internet — including retail apparel, retail general merchandise, healthcare items, automobile parts, airline baggage, food and much more. With more than 100 billion items connected to date, and multiple Fortune 500 enterprises around the world using our platform, we solve for a better understanding of our world. If it’s a thing, we’re working to connect it. Join Impinj and help us realize our vision of a boundless IoT— connecting trillions of everyday items to the Internet. Team Overview The RAIN Reader IC (RIC) design group is part of the Impinj Silicon Engineering department and is responsible for the development of Impinj’s RIC products. Within the RIC Design group, the digital team owns the digital subsystems of these products, including the digital modem, the microcontroller subsystem, digital control loops, calibration engines, and the control and interface logic for analog IP. The team carries these designs from architecture and micro-architecture definition through RTL, verification, DFT, and timing closure to tapeout, post-silicon bring-up, and validation, partnering closely with chip architects, RF/analog designers, physical design, and CAD/EDA engineers and using state-of-the-art tools and methodologies. The team works to balance short-term goals needed to deliver products rapidly to market and long-term enhancements to methodologies and practices to enable future efficiencies.

Requirements

Bachelor’s degree in Electrical or Computer Engineering, with 12 years of experience (or 8 years with MS or 5 years with a PhD) required
12+ years of experience in RTL verification.
Experience in the verification of microcontroller microarchitectures and complex finite-state machines.
Experience creating and implementing RTL functional verification test plans.
Experience defining and developing bus functional models, subsystem behavioral models and architectural checkers.
Expertise in SystemVerilog and the Universal Verification Methodology (UVM).
Hands-on experience developing SV assertions, re-usable sequences, and coverage monitors.
Proven ability to bring complex designs from concept through tape-out and production.
Familiarity with CI/CD systems and RTL coverage tools.
Scripting proficiency in Perl, Python, Ruby, or UNIX shell.
Excellent written and verbal communication skills.

Responsibilities

Contribute to verification of Impinj’s next-generation RAIN RFID Reader ICs through all phases of product development.
Define and develop state-of-the-art verification methodologies and infrastructure
Develop bus functional models, subsystem behavioral models, RTL code, and SystemVerilog testbenches.
Write and execute directed and constrained-random tests to achieve comprehensive functional coverage.
Define verification coverage metrics to evaluate and guarantee the tape-out of high-quality IC designs
Create SystemVerilog assertions, coverage monitors, and detailed test plans for features and functional blocks.
Enhance verification efficiency by developing CI/CD workflows and custom toolkits for automation and reporting.
Collaborate across logic, analog, test, and systems engineering teams to deliver new features and products to market.
Support continuous improvement of existing RAIN RFID products through feature and performance enhancements.