Staff SoC RTL Engineer

quadric.io•Burlingame, CA

1d•Onsite

About The Position

Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems. Founded by technologists from MIT and Carnegie Mellon, Quadric is a well-funded growth-stage semiconductor IP company with a growing licensing business. As we enter our next phase of growth, we're looking for our first true marketing leader to build and scale the function. The Opportunity Quadric is building a revolutionary new processor-based SoC architecture. As a Staff SoC RTL Engineer , you will get in on the ground floor as a key member of our chip design team, contributing across all stages of the SoC design and integration cycle. In this role, you will help define the SoC architecture, own subsystem development, integrate third-party IP, and drive PPA optimization to bring our next-generation platform to life.

Requirements

BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience.
Proficiency in SystemVerilog or Verilog.
Strong background in computer architecture, low-power digital design techniques, and deep technical knowledge in at least one subsystem (Memory, I/O, or Compute).
Proven experience with SoC subsystems (including 3rd-party IP) and working knowledge of VCS & Verilog/C Co-Simulation.

Nice To Haves

Experience in logic synthesis and performance modeling.
Experience in FPGA design.
Familiarity with automotive safety standards (ASIL) and hardware security standards.

Responsibilities

Own SoC-level subsystem development and seamless integration with third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
Contribute directly to the definition of the SoC architecture by deeply understanding its application requirements.
Package designs for customer releases and rapidly iterate based on customer feedback.
Own Power, Performance, and Area (PPA) optimization strategies at the SoC level.
Apply low-power digital design techniques to optimize hardware efficiency.
Contribute to timing closure across the full product lifecycle, spanning front-end, back-end, and final tapeout stages.
Balance single-stream latency against scaled throughput performance.